JPH0481335B2 - - Google Patents
Info
- Publication number
- JPH0481335B2 JPH0481335B2 JP57005918A JP591882A JPH0481335B2 JP H0481335 B2 JPH0481335 B2 JP H0481335B2 JP 57005918 A JP57005918 A JP 57005918A JP 591882 A JP591882 A JP 591882A JP H0481335 B2 JPH0481335 B2 JP H0481335B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- integrated circuit
- ion implantation
- metal wiring
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 26
- 238000005468 ion implantation Methods 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 46
- 229910052751 metal Inorganic materials 0.000 description 28
- 239000002184 metal Substances 0.000 description 28
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 18
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 17
- 239000000463 material Substances 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明はガリウム砒素基板もしくは半絶縁性基
板を用いた集積回路に係り、特に集積回路上に形
成された金属配線のクロストーク雑音および寄生
容量低減に適した配線構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit using a gallium arsenide substrate or a semi-insulating substrate, and more particularly to a wiring structure suitable for reducing crosstalk noise and parasitic capacitance of metal wiring formed on an integrated circuit. .
化合物半導体ガリウム砒素（GaAs）を用いた
半導体デバイスは、シリコン（Si）を用いた半導
体デバイスと比較して、電子移動度が大きく、ま
た絶縁性のGaAs基板上に素子を形成するため寄
生容量が小さいこと等の特長があり、本質的に高
速動作に適している。特に近年シヨツトキ・バリ
ア・ゲート形の電界効果トランジスタをGaAs基
板上に集積化した高速論理集積回路が注目され始
めている。第１図にこのようなGaAs集積回路の
断面の一例を示す。図において、１００はGaAs
半絶縁性基板、１０１〜１０３はそれぞれシヨツ
トキ・バリア・ゲート形電界効果トランジスタの
ソース、ゲート、ドレイン電極である。また１０
４，１０６は高濃度トランジスタ打込層、１０５
は電界効果トランジスタのチヤネル部形成用の低
濃度イオン打込層である。電極１０１，１０３
は、たとえば、金（Au）・ゲルマニウム（Ge）
合金等を材料とし、高濃度イオン打込層１０４，
１０６と抵抗性接触を形成している。また電極１
０２は、たとえば、アルミニウム（Al）等を材
料とし、低濃度イオン打込層１０５とシヨツトキ
接合を形成している。なお、イオン打込層１０４
〜１０６を形成するための不純物は、Ｎ型の導電
性を示す、たとえばシリコン（Si）等が用いられ
ている。GaAs基板上に集積されたシヨツトキ・
バリア・ゲート形電界効果トランジスタ等の素子
を接続するために１０７〜１１２の金属配線が形
成される。これらはGaAs基板上に直接接触して
設けられた第１の金属配線層１０７〜１１０と、
層間絶縁膜１１３を介して第１の金属配線層より
さらに上層に位置する第２の金属配線層１１１，
１１２に分類される。第１の金属配線は一般に電
界効果トラジスタのソース、ドレイン電極または
ゲート電極と同一の材質で形成される。第２の金
属配線層は、たとえば、金（Au）・モリブデン
（Mo）合金等を材料とし、第１の金属配線と直
交、あるいは平行して形成される。１１３は層間
絶縁膜であり、材質としては、たとえば酸化シリ
コン（SiO2）が用いられる。ここで１０７〜１
１２で示す金属配線に高速パルス信号を伝送する
ことを考える。従来の、たとえばシリコン集積回
路の場合は、基板が導電性を示すために金属配線
に対してグランドとして作用するので、高速パル
ス信号のリターンパスとなる。しかし、GaAs集
積回路等では基板が導電性を示さないためにリタ
ーンパスとして働らかず、すぐ近くを通つている
金属配線（例えば１０８に対して１０７と１０９
等）を伝わつて高速パルス信号が戻つてくる。こ
のためにGaAs集積回路等では金属配線間のクロ
ストーク雑音が問題となる。また、第１層の金属
配線間の容量についても、GaAs基板の比誘電率
が約11.4と大きいためにあまり小さくはならず、
シリコン集積回路の場合とほぼ同じ程度となる。 Semiconductor devices using the compound semiconductor gallium arsenide (GaAs) have higher electron mobility than semiconductor devices using silicon (Si), and because the elements are formed on an insulating GaAs substrate, parasitic capacitance is reduced. It has features such as being small and is inherently suitable for high-speed operation. In particular, in recent years, high-speed logic integrated circuits that integrate field effect transistors of the Schottky barrier gate type on GaAs substrates have begun to attract attention. FIG. 1 shows an example of a cross section of such a GaAs integrated circuit. In the figure, 100 is GaAs
The semi-insulating substrates 101 to 103 are the source, gate, and drain electrodes of a shot barrier gate field effect transistor, respectively. 10 more
4, 106 is a high concentration transistor implantation layer, 105
is a low concentration ion implantation layer for forming a channel portion of a field effect transistor. Electrodes 101, 103
For example, gold (Au), germanium (Ge)
The high concentration ion implantation layer 104 is made of an alloy or the like.
It forms resistive contact with 106. Also, electrode 1
02 is made of, for example, aluminum (Al) or the like, and forms a shot junction with the low concentration ion implantation layer 105. Note that the ion implantation layer 104
As the impurity for forming .about.106, silicon (Si) or the like, which exhibits N-type conductivity, is used. A shotgun integrated on a GaAs substrate.
Metal interconnections 107 to 112 are formed to connect elements such as barrier gate field effect transistors. These include first metal wiring layers 107 to 110 provided in direct contact with the GaAs substrate;
A second metal wiring layer 111 located further above the first metal wiring layer via an interlayer insulating film 113,
It is classified as 112. The first metal wiring is generally made of the same material as the source, drain, or gate electrode of the field effect transistor. The second metal wiring layer is made of, for example, a gold (Au)/molybdenum (Mo) alloy, and is formed perpendicularly or parallel to the first metal wiring. Reference numeral 113 denotes an interlayer insulating film, and its material is, for example, silicon oxide (SiO 2 ). Here 107-1
Consider transmitting a high-speed pulse signal to the metal wiring indicated by 12. In the case of conventional silicon integrated circuits, for example, the substrate exhibits conductivity and thus acts as a ground for metal wiring, thus serving as a return path for high-speed pulse signals. However, in GaAs integrated circuits, etc., the substrate does not exhibit conductivity, so it does not function as a return path, and the metal wiring passing nearby (for example, 107 and 109 instead of 108) does not function as a return path.
etc.) and the high-speed pulse signal returns. For this reason, crosstalk noise between metal wirings becomes a problem in GaAs integrated circuits and the like. In addition, the capacitance between the first layer metal interconnects does not decrease much because the dielectric constant of the GaAs substrate is as large as approximately 11.4.
This is approximately the same level as in the case of silicon integrated circuits.
本発明は、従来の配線構造が有する前記欠点を
解消するためになされたもので、その目的は配線
間のクロストーク雑音および寄生容量を低減する
新規な配線構造を有する半導体集積回路を提供す
ることにある。 The present invention has been made to eliminate the above-mentioned drawbacks of conventional wiring structures, and its purpose is to provide a semiconductor integrated circuit having a novel wiring structure that reduces crosstalk noise and parasitic capacitance between wirings. It is in.
かかる目的を達成するため、本発明は、集積回
路を構成するために半絶縁性基板に設けられた複
数の回路素子と、半絶縁性基板上に設けられ、回
路素子間を接続するために、互いに近接して略平
行に配置された複数の配線を有する第１層の配線
とを備えた半導体集積回路において半絶縁性基板
と第１層の配線との間に設けられた絶縁膜と第１
層の配線のうち少なくとも互いに近接して略平行
に配置された複数の配線下の半絶縁性基板内に形
成された低インピーダンスの活性層とを備えたこ
とを特徴とする。 In order to achieve such an object, the present invention provides a plurality of circuit elements provided on a semi-insulating substrate to configure an integrated circuit, and a plurality of circuit elements provided on the semi-insulating substrate to connect the circuit elements. In a semiconductor integrated circuit comprising a first layer of wiring having a plurality of wirings arranged close to each other and substantially parallel, an insulating film provided between a semi-insulating substrate and the first layer of wiring;
It is characterized by comprising a low impedance active layer formed in a semi-insulating substrate under at least a plurality of wirings arranged close to each other and substantially parallel among the wirings in the layer.
以下、第２図および第３図を用いて、GaAs集
積回路を例にとつて本発明の実施例を説明する。
第２図において、第１層の金属配線１０７〜１１
０はGaAs基板１００上に設けられた絶縁膜１１
４上に配置され、直接基板１００に接触しないよ
うになつている。さらに第１層の金属配線１０７
〜１１０下の基板１００にはイオン打込層１１５
が形成されている。このような配線構造にするこ
とにより、金属配線間のクロストーク雑音および
寄生容量を低減することが可能となる。すなわ
ち、本構造では、例えば金属配線１０８を通る高
速パルス信号のリターンパスが、第１図の従来例
と異なり、イオン打込層１１５となるからであ
る。また金属配線の下の絶縁膜１１４の比誘電率
をGaAs基板１００の比誘電率よりも小さくする
ことにより、金属配線間の寄生容量も寄生容量も
低減することができる。さらに、第３図に示すよ
うにイオン打込層１１５の下に１１５とは逆の導
電性を示すイオン打込層１１６をもうけ、イオン
打込層１１５と１１６から形成されるPN接合ダ
イオードが逆バイアスになるようにイオン打込層
１１６の電位を固定することにより、金属配線の
寄生容量を第２図の実施例よりもさらに低減する
ことができる。すなわち金属配線層１０７〜１１
０と第１のイオン打込層１１５との間の容量と、
第１のイオン打込層１１５と第２のイオン打込層
１１６により形成されるPN接合ダイオードの逆
バイアスの容量とが直列接続されて、金属配線と
電源の間に入るためである。 Embodiments of the present invention will be described below using FIGS. 2 and 3, taking a GaAs integrated circuit as an example.
In FIG. 2, first layer metal wiring 107 to 11
0 is an insulating film 11 provided on a GaAs substrate 100
4 and not in direct contact with the substrate 100. Furthermore, the first layer metal wiring 107
The substrate 100 below ~110 has an ion implantation layer 115.
is formed. By adopting such a wiring structure, it becomes possible to reduce crosstalk noise and parasitic capacitance between metal wirings. That is, in this structure, the return path of a high-speed pulse signal passing through, for example, the metal wiring 108 is the ion implantation layer 115, unlike the conventional example shown in FIG. Further, by making the dielectric constant of the insulating film 114 under the metal wiring smaller than that of the GaAs substrate 100, the parasitic capacitance between the metal wiring and the parasitic capacitance can be reduced. Furthermore, as shown in FIG. 3, an ion implantation layer 116 having conductivity opposite to that of ion implantation layer 115 is provided below the ion implantation layer 115, so that the PN junction diode formed from the ion implantation layers 115 and 116 is reversed. By fixing the potential of the ion implantation layer 116 so as to provide a bias, the parasitic capacitance of the metal wiring can be further reduced than in the embodiment shown in FIG. That is, metal wiring layers 107 to 11
0 and the first ion implantation layer 115;
This is because the reverse bias capacitance of the PN junction diode formed by the first ion implantation layer 115 and the second ion implantation layer 116 is connected in series and placed between the metal wiring and the power supply.
なお、第１層金属配線下の絶縁膜１１４の材質
は、第１層金属配線と第２層金属配線の間の絶縁
膜１１３の材質と同じであつても、あるいはまつ
たく別の材質であつてもかまわない。本質的に
は、基剤材質よりも比誘電率が低く、電気的に絶
縁可能な材質であればよい。このような絶縁膜の
材料としては、SiO2、PSG、PIQ等を用いること
ができ、その膜厚としては3000Å〜6000Å程度が
好ましい。 Note that the material of the insulating film 114 under the first layer metal wiring may be the same as the material of the insulating film 113 between the first layer metal wiring and the second layer metal wiring, or it may be a different material. It doesn't matter. Essentially, any material may be used as long as it has a dielectric constant lower than that of the base material and can be electrically insulated. As a material for such an insulating film, SiO 2 , PSG, PIQ, etc. can be used, and the film thickness is preferably about 3000 Å to 6000 Å.
また、イオン打込層１１５の導電性はＰ型であ
つてもＮ型であつてもよい。さらに、その下に第
２のイオン打込層をもうける場合は、第１のイオ
ン打込層と逆の導電性を示すものであればよい。
Ｐ型の導電性を示すイオン打込層を形成するため
の不純物としては、マグネシウム（Mg）、ベリ
ウム（Be）、アエン（Zn）等を用いることがで
き、Ｎ型の導電性を示すイオン打込層を作成する
ための不純物としては、シリコン（Si）、セレン
（Se）、イオン（Ｓ）等を用いることができる。
これらのイオン打込層の膜厚としては、2000Å〜
5000Å程度が好ましい。なお、これらのイオン打
込層は、本質的には抵抗率が数100Ω／cm3以下で
あるような低インピーダンス特性を示す活性層で
あればよいので、拡散等の手段で形成してもよ
い。 Further, the conductivity of the ion implantation layer 115 may be P type or N type. Furthermore, when forming a second ion implantation layer thereunder, it is sufficient if the second ion implantation layer exhibits conductivity opposite to that of the first ion implantation layer.
Magnesium (Mg), beryum (Be), aene (Zn), etc. can be used as impurities to form an ion implantation layer that exhibits P-type conductivity; Silicon (Si), selenium (Se), ions (S), etc. can be used as impurities for creating the embedded layer.
The film thickness of these ion implantation layers is 2000Å~
Approximately 5000 Å is preferable. Note that these ion-implanted layers may be formed by means such as diffusion, as they essentially only need to be active layers that exhibit low impedance characteristics with a resistivity of several 100 Ω/cm 3 or less. .
以上説明したように、本発明によれば、第１層
の金属配線下に基板材料よりも比誘電率の低い材
質の絶縁層を配置し、さらにその下の基板に１層
または２層のイオン打込層をもうけることによ
り、金属配線間のクロストーク雑音を低減できる
と共に、寄生容量も低減することができる。これ
により、集積回路の高速動作を達成できる効果が
ある。 As explained above, according to the present invention, an insulating layer made of a material with a dielectric constant lower than that of the substrate material is disposed under the first layer of metal wiring, and one or two layers of ion are further disposed on the substrate below the insulating layer. By providing an implantation layer, crosstalk noise between metal wirings can be reduced, and parasitic capacitance can also be reduced. This has the effect of achieving high-speed operation of the integrated circuit.
しかも、本発明は、従来の製造工程にフオトマ
スクを１枚（第３図の構造にする場合は２枚）を
追加するだけで容易に実現でき、製造工程に大幅
な変更を必要としない。 Furthermore, the present invention can be easily realized by simply adding one photomask (two in the case of the structure shown in FIG. 3) to the conventional manufacturing process, and does not require any major changes to the manufacturing process.
なお、本発明の適用範囲は上述したGaAs集積
回路にとどまらず、基板が半絶縁性を示すような
集積回路であれば適用可能である。 Note that the scope of application of the present invention is not limited to the above-mentioned GaAs integrated circuit, but can be applied to any integrated circuit whose substrate exhibits semi-insulating properties.
第１図は従来のGaAs集積回路の構造を示す断
面図、第２図は本発明によるGaAs集積回路の一
実施例の断面図、第３図は本発明の他の実施例を
示す断面図である。
１００……GaAs基板、１０７〜１１０……金
属配線、１１４……絶縁膜、１１５……第１のイ
オン打込層、１１６……第２のイオン打込層。
FIG. 1 is a cross-sectional view showing the structure of a conventional GaAs integrated circuit, FIG. 2 is a cross-sectional view of one embodiment of the GaAs integrated circuit according to the present invention, and FIG. 3 is a cross-sectional view showing another embodiment of the present invention. be. 100... GaAs substrate, 107-110... Metal wiring, 114... Insulating film, 115... First ion implantation layer, 116... Second ion implantation layer.
Claims (1)
けられた複数の回路素子と、上記半絶縁性基板上
に設けられ、上記回路素子間を接続するために、
互いに近接して略平行に配置された複数の配線を
有する第１層の配線とを備えた半導体集積回路に
おいて、 上記半絶縁性基板と上記第１層の配線との間に
設けられた絶縁膜と、 上記第１層の配線のうち少なくとも互いに近接
して略平行に配置された複数の配線下の上記半絶
縁性基板内に形成された低インピーダンスの活性
層とを備えたことを特徴とする半導体集積回路。 ２ 上記活性層がイオン打込により形成されてな
ることを特徴とする特許請求の範囲第１項記載の
半導体集積回路。 ３ 上記活性層が互いに逆の導電性を有する２つ
のイオン打込層からなることを特徴とする特許請
求の範囲第１項に記載の半導体集積回路。[Claims] 1. A plurality of circuit elements provided on a semi-insulating substrate to constitute an integrated circuit, and a plurality of circuit elements provided on the semi-insulating substrate for connecting the circuit elements,
A semiconductor integrated circuit comprising a first layer of wiring having a plurality of wirings arranged close to each other and substantially parallel, an insulating film provided between the semi-insulating substrate and the first layer of wiring. and a low impedance active layer formed in the semi-insulating substrate under at least a plurality of wirings arranged close to each other and substantially parallel among the wirings of the first layer. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the active layer is formed by ion implantation. 3. The semiconductor integrated circuit according to claim 1, wherein the active layer comprises two ion-implanted layers having mutually opposite conductivities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP591882A JPS58123753A (en) | 1982-01-20 | 1982-01-20 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP591882A JPS58123753A (en) | 1982-01-20 | 1982-01-20 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58123753A JPS58123753A (en) | 1983-07-23 |
| JPH0481335B2 true JPH0481335B2 (en) | 1992-12-22 |
Family
ID=11624267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP591882A Granted JPS58123753A (en) | 1982-01-20 | 1982-01-20 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58123753A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0624223B2 (en) * | 1983-12-09 | 1994-03-30 | 株式会社東芝 | Microwave integrated circuit device |
| JPH07120706B2 (en) * | 1986-06-27 | 1995-12-20 | 日本電信電話株式会社 | Wiring structure of semiconductor integrated circuit |
| US5942773A (en) * | 1996-06-04 | 1999-08-24 | Fujitsu Limited | Field effect transistor with reduced delay variation |
| JP3416537B2 (en) | 1998-11-13 | 2003-06-16 | 富士通カンタムデバイス株式会社 | Compound semiconductor device and method of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5141977A (en) * | 1974-10-07 | 1976-04-08 | Suwa Seikosha Kk | HANDOTA ISOCHI |
| JPS5643757A (en) * | 1979-09-18 | 1981-04-22 | Nec Corp | Gallium arsenic type integrated circuit |
-
1982
- 1982-01-20 JP JP591882A patent/JPS58123753A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5141977A (en) * | 1974-10-07 | 1976-04-08 | Suwa Seikosha Kk | HANDOTA ISOCHI |
| JPS5643757A (en) * | 1979-09-18 | 1981-04-22 | Nec Corp | Gallium arsenic type integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58123753A (en) | 1983-07-23 |
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