JPS63150957A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63150957A JPS63150957A JP61296683A JP29668386A JPS63150957A JP S63150957 A JPS63150957 A JP S63150957A JP 61296683 A JP61296683 A JP 61296683A JP 29668386 A JP29668386 A JP 29668386A JP S63150957 A JPS63150957 A JP S63150957A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- region
- electrode
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000010410 layer Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は、縦形ＭＯＳトランジスタと、その制御回路
等を構成する他の半導体素子とのｉｍ化に適した半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device suitable for IM integration of a vertical MOS transistor and other semiconductor elements constituting its control circuit and the like.
〈従来の技術）
近年、各種車載用電力負荷等のスイッチング素子として
縦形ＭＯＳトランジスタが使用されている。<Prior Art> In recent years, vertical MOS transistors have been used as switching elements for various vehicle-mounted power loads and the like.
このような従来の縦形ＭＯＳトランジスタとしては、例
えば第３図に示すようなものがある（エレクトロニクス
、昭和５７年６月、ｐ５８７）。An example of such a conventional vertical MOS transistor is the one shown in FIG. 3 (Electronics, June 1987, p. 587).
第３図中、３１はＮ４基板であり、Ｎ１基板３１上にＮ
ドレイン領域３２が形成されている。Ｎドレイン領域３
２の表面側には、Ｐウェル領域３３が形成され、このＰ
ウェル領域３３内にＮ＋ンース領ｆ４３４が形成されて
いる。In FIG. 3, 31 is an N4 substrate, and N1 is placed on the N1 substrate 31.
A drain region 32 is formed. N drain region 3
A P well region 33 is formed on the surface side of the P well region 2.
An N+ region f434 is formed within the well region 33.
またＮ＋ソース領域３４およびＮドレイン領域３２間に
おけるＰウェル領域３３上には、このＰウェル領域３３
の表面層にチャネル３５を誘起させるためのゲート電極
３６が、ゲート絶縁膜３７を介して設けられている。Moreover, on the P well region 33 between the N+ source region 34 and the N drain region 32, this P well region 33
A gate electrode 36 for inducing a channel 35 in the surface layer is provided with a gate insulating film 37 interposed therebetween.
３８は層間絶縁膜、３９はソース電極であり、ソース電
極３９はＮ＋ソース領域３４およびＰウェル領域３３に
接続されている。またＮ＋基板３１の裏面にはドレイン
電極４０が形成されている。38 is an interlayer insulating film, 39 is a source electrode, and the source electrode 39 is connected to the N+ source region 34 and the P well region 33. Further, a drain electrode 40 is formed on the back surface of the N+ substrate 31.
そしてドレイン電極４０に所要値の正電圧が加えられ、
ゲート電極３６に閾値電圧以上のゲート電圧が加えられ
ると、チャネル３５が導通してドレイン・ソース間に電
流Ｂが流れる。Then, a required positive voltage is applied to the drain electrode 40,
When a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 36, the channel 35 becomes conductive and a current B flows between the drain and the source.
縦形ＭＯＳトランジスタは通常のＭＯＳトランジスタの
持つ長所に加え、低オン抵抗で、高耐圧化、大電流容量
化が容易であり、近年ＭＯ８形パワートランジスタの主
流となりつつあるものである。In addition to the advantages of normal MOS transistors, vertical MOS transistors have low on-resistance, high breakdown voltage, and easy to increase current capacity, and have recently become the mainstream MO8 type power transistor.
上述のような縦形ＭＯＳトランジスタを用いて負荷を駆
ｆ）ノする場合、ソース電極３９を接地して負荷をドレ
イン電極４０に接続する負荷トレイン側方式と、負荷を
ソース側に接続するソースフォロワ方式とがある。When driving a load using a vertical MOS transistor as described above, there are two methods: a load train side method where the source electrode 39 is grounded and the load is connected to the drain electrode 40, and a source follower method where the load is connected to the source side. There is.
負荷ドレイン側方式では、動作中にドレイン電極４０、
即ちＮ＋基板３１の電位が接地電位近くから電源電圧ま
で大きく変化する。In the load drain side method, the drain electrode 40,
That is, the potential of the N+ substrate 31 changes greatly from near the ground potential to the power supply voltage.
一方、ソースフォロワ方式では、ドレイン電極４０の電
位は電源電圧に固定されるが、縦形ＭＯ８］−ランジス
タがオン状態のときソース電極３つの電位は電源電ＬＬ
に近くなる。したがってゲート・ソース間電圧を十分確
保するためには、ゲートＦＦ電極３６の電圧は電源電圧
よりも高くすることが必要であり、このため昇圧回路等
の付設が必要とされる。On the other hand, in the source follower method, the potential of the drain electrode 40 is fixed to the power supply voltage, but when the vertical MO8]- transistor is in the on state, the potential of the three source electrodes is fixed to the power supply voltage LL.
It becomes close to. Therefore, in order to ensure a sufficient gate-source voltage, it is necessary to make the voltage of the gate FF electrode 36 higher than the power supply voltage, and therefore a booster circuit or the like is required.
（発明が解決しようとする問題点）
ところで縦形ＭＯＳトランジスタを動作させるためには
制御回路が必要であり、このような制御回路を含む処理
回路をその縦形ＭＯＳトランジスタと同一チップ中に集
積化すれば、装置寸法の縮小、実装コストの低減、中間
配線の省略によるコスト低減および性能向上等が考えら
れる。(Problem to be solved by the invention) By the way, a control circuit is necessary to operate a vertical MOS transistor, and if a processing circuit including such a control circuit is integrated on the same chip as the vertical MOS transistor, , reduction in device size, reduction in mounting cost, cost reduction and performance improvement due to omission of intermediate wiring, etc. can be considered.
また縦形ＭＯＳトランジスタの使用される回路方式によ
っては、マルチトレインとして同一チップ上に複数個の
縦形ＭＯＳトランジスタの形成されたものが望まれる場
合がある。Further, depending on the circuit system in which the vertical MOS transistors are used, it may be desired to form a plurality of vertical MOS transistors on the same chip as a multi-train.
しかしながら前述した従来の縦形ＭＯＳトランジスタに
あっては、Ｎ＋基板３１側がドレインとなっていたため
、負荷トレイン側方式で使用すると、動作時にその基板
電位が接地電位近くから電源電圧まで大ぎく振れるので
、同一基板上に制御回路を含む他の処理回路等を集積化
できず、またマルチトレインとすることができないので
、同一チップ上に複数個の縦形ＭＯＳトランジスタを形
成することができないという問題点があった。However, in the conventional vertical MOS transistor mentioned above, the drain is on the N+ substrate 31 side, so when used in the load train side method, the substrate potential swings sharply from near the ground potential to the power supply voltage during operation, making it difficult to maintain the same level. Since other processing circuits including control circuits cannot be integrated on the substrate, and multi-trains cannot be formed, there is a problem that multiple vertical MOS transistors cannot be formed on the same chip. .
また動作時における基板電位の変動を避けるため、ソー
スフォロワ方式で使用すると、昇圧回路の付設が必要と
なって処理回路が複雑化するという問題点があった。Furthermore, if a source follower method is used in order to avoid fluctuations in substrate potential during operation, a booster circuit must be added, complicating the processing circuit.
この発明は、このような従来の問題点に着目してなされ
たもので、縦形ＭＯＳトランジスタおよびその制御１回
路等を構成する他の半導体素子を同一チップ上に容易に
集積化することができ、また同一チップ上に複数個の縦
形ＭＯＳトランジスタを形成することのできる半導体装
置を提供することを目的とする。The present invention has been made in view of these conventional problems, and it is possible to easily integrate a vertical MOS transistor and other semiconductor elements constituting its control circuit on the same chip. Another object of the present invention is to provide a semiconductor device in which a plurality of vertical MOS transistors can be formed on the same chip.
［発明の構成］
（問題点を解決するための手段）
この発明は上記問題点を解決するために、第１導電形の
基板と、該基板上に形成された第２導電形層と、該第２
導電形層に形成され前記基板に接続される第１導電形の
ウェル領域と、該ウェル領域内に形成゛された第２導電
形のドレイン領域と、該ドレイン領域と前記第２導電形
層で形成されるソース領域との間の前記ウェル領域上に
ゲート絶縁膜を介して設けられ当該ウェル領域にチャネ
ルを誘起させるゲート電極と、前記基板のπ面に穿設さ
れた溝により前記ソース領域および前記基板に接続され
るソース電極とを有することを要旨とする。[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention includes a substrate of a first conductivity type, a layer of a second conductivity type formed on the substrate, and a layer of a second conductivity type formed on the substrate. Second
a well region of a first conductivity type formed in a conductivity type layer and connected to the substrate; a drain region of a second conductivity type formed in the well region; and a drain region formed in the drain region and the second conductivity type layer. A gate electrode is provided on the well region between the source region to be formed via a gate insulating film and induces a channel in the well region, and a groove is formed in the π-plane of the substrate to connect the source region and and a source electrode connected to the substrate.
（作用）
負荷駆動方式として、ソース電極を接地して負荷をドレ
イン領域側に接続する負荷トレイン側方式としたとき、
基板は、ソース電極に接続されて常時接地電位に保持さ
れるので電位の変動が生じない。(Function) When the load drive method is a load train side method in which the source electrode is grounded and the load is connected to the drain region side,
The substrate is connected to the source electrode and is always held at ground potential, so potential fluctuations do not occur.
したがって同一の基板上に当該縦形ＭｏＳトランジスタ
の制御回路を含む他の処理回路等を集積化することが容
易とされる。Therefore, it is easy to integrate other processing circuits including a control circuit for the vertical MoS transistor on the same substrate.
（実施例） 以下、この発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described below based on the drawings.
第１図は、この発明の一実施例を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.
まず構成を説明すると、第１図中、１は第１導電形のＰ
＋基板であり、Ｐ＋基板１上に第２１３雷形のＮ形層２
が形成されている。First, to explain the configuration, in FIG. 1, 1 is P of the first conductivity type.
+ substrate, and the 213th lightning-shaped N-type layer 2 is on the P+ substrate 1.
is formed.
上記のようにＰ形を第１導電形としたとき、これと反対
導電形のＮ形は第２導電形となる。When the P type is set as the first conductivity type as described above, the N type, which is the opposite conductivity type, becomes the second conductivity type.
Ｎ形層２の所要位置には、Ｐウェル領［５が形成されて
いる。Ｐウェル領域５は、その底部がＰ１基板連結領域
６によりＰ＋基板１に接続されている。Ｐウェル領域５
およびＰ＠基板連結領域６の形成された部分以外のＮ形
層２によりＮソース領域３が形成される。Ｎソースｆ［
３とＰ＋基板１の界面部には選択的にＮ＋ソース領Ｔａ
４が形成されている。A P-well region [5 is formed at a predetermined position of the N-type layer 2. The bottom of the P well region 5 is connected to the P+ substrate 1 by a P1 substrate connection region 6. P well area 5
An N source region 3 is formed by the N type layer 2 other than the portion where the P@substrate connection region 6 is formed. N source f [
3 and the P+ substrate 1, an N+ source region Ta is selectively formed.
4 is formed.
そしてＰウェル領域５内にＮ＋ドレイン領域７が形成さ
れている。またＮ＋ドレイン領域７およびＮソース領域
３間におけるＰウェル領域５上には、このＰウェル領域
５の表面層にチャネル８を誘起させるためのゲート電極
９が、ゲート酸化膜（絶縁ＩＢ２）１１を介して形成さ
れている。An N+ drain region 7 is formed within the P well region 5. Further, on the P well region 5 between the N+ drain region 7 and the N source region 3, a gate electrode 9 is provided to induce a channel 8 in the surface layer of the P well region 5. formed through.
１２は層間絶縁膜であり、この層間絶縁膜１２の形成さ
れた表面側に、Ｎ＋ドレイン領域７に接続されたドレイ
ン電極１３が設けられている。12 is an interlayer insulating film, and a drain electrode 13 connected to the N+ drain region 7 is provided on the surface side where the interlayer insulating film 12 is formed.
またＰ＋基板１の裏面には、断面が逆Ｖ字状の溝１４が
エツチング加工により穿設され、この溝１４によりＮ＋
ソース領域４に接続されるとともに、Ｐ＋基板１にも接
続されたソース電極１６が形成されている。Further, on the back surface of the P+ substrate 1, a groove 14 having an inverted V-shaped cross section is formed by etching.
A source electrode 16 connected to the source region 4 and also connected to the P+ substrate 1 is formed.
上述のように、縦形ＭＯＳトランジスタは、そのＮ＋ド
レイ、ン領域７が、チップ表面側のＰウェル領域５内に
それぞれ形成され、Ｐ＋基板１がソース側とされるので
、マルヂドレインとすることが可能であり、同一チップ
上に複数個の縦形ＭＯＳトランジスタを形成することが
容易とされる。As mentioned above, in the vertical MOS transistor, the N+ drain and N regions 7 are formed in the P well region 5 on the chip surface side, and the P+ substrate 1 is on the source side, so it can be used as a multi-drain. This makes it easy to form a plurality of vertical MOS transistors on the same chip.
次に作用を説明する。Next, the action will be explained.
ドレイン電極１３に所要値の正電圧が加えられ、ゲート
電極９に閾値電圧以上のゲート電圧が加えられると、チ
ャネル８が導通し、電流Ａがドレイン電極１３、Ｎ＋ド
レイン領域７、チャネル８、Ｎソース領域３およびＮ＋
ソース領域４を経てソース電極１６に流れる。When a required positive voltage is applied to the drain electrode 13 and a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 9, the channel 8 becomes conductive and the current A flows through the drain electrode 13, the N+ drain region 7, the channel 8, and the N+ drain region 7. Source region 3 and N+
It flows to the source electrode 16 via the source region 4 .
そして負荷駆動方式として、ソース電極１６を接地して
負荷をドレイン電極１３に接続する負荷トレイン側方式
としても、Ｐ＋基板１は、ソース電極１６に接続されて
常時接地電位に保持されているので電位の変動が生じな
い。As a load drive method, even if the load train side method is used in which the source electrode 16 is grounded and the load is connected to the drain electrode 13, the P+ substrate 1 is connected to the source electrode 16 and is always held at the ground potential. No fluctuation occurs.
したがって同一の基板１上に当該縦形ＭＯＳトランジス
タの制御回路を含む他の処理回路等を集積化することが
可能とされる。Therefore, it is possible to integrate other processing circuits including a control circuit for the vertical MOS transistor on the same substrate 1.
次いで第２図には、この発明の伯の実施例を示す。Next, FIG. 2 shows an embodiment of the present invention.
この実施例は、縦形ＭｏＳトランジスタと、この縦形Ｍ
ＯＳトランジスタの処理回路等を構成するトランジスタ
素子等を同一チップ上に形成したものである。This embodiment uses a vertical MoS transistor and the vertical M
Transistor elements constituting an OS transistor processing circuit and the like are formed on the same chip.
なお、第２図において前記第１図における部材または部
位等と同一ないし均等のものは、前記と同一符号を以っ
て示し重複した説明を省略する。In FIG. 2, parts that are the same as or equivalent to those in FIG. 1 are designated by the same reference numerals and redundant explanations will be omitted.
この実施例では、縦形ＭＯＳトランジスタ１０の部分に
おけるＰウェル領域１５は、その底部が直接Ｐ＋基板１
に接続されるように深く形成されている。In this embodiment, the P well region 15 in the vertical MOS transistor 10 has its bottom directly connected to the P+ substrate 1.
It is deeply formed so that it is connected to the
そしてＰ＋基板１およびＮ形層２の延在した部分に、処
理回路２０を構成するＮＭＯＳトランジスタ１８および
ＰＭＯ８）−ランジスタ１９が形成されている。なお処
理回路２０の構成素子としては、ＮＭＯＳトランジスタ
１８およびＰＭＯＳトランジスタ１９以外の素子も適宜
に形成される。An NMOS transistor 18 and a PMO transistor 19, which constitute the processing circuit 20, are formed in the extended portion of the P+ substrate 1 and the N-type layer 2. Note that as constituent elements of the processing circuit 20, elements other than the NMOS transistor 18 and the PMOS transistor 19 are also formed as appropriate.
縦形ＭＯＳトランジスタ１０と、処理回路２０を構成す
るＮＭＯＳトランジスタ１８およびＰＭＯＳトランジス
タ１９の形成領域どの間には、１）＋基板１に遼するＰ
形ガードリング１７が縦形ＭＯＳトランジスタ１０を囲
むように形成されている。Between the formation regions of the vertical MOS transistor 10 and the NMOS transistor 18 and PMOS transistor 19 constituting the processing circuit 20, there are 1) + P connected to the substrate 1;
A shaped guard ring 17 is formed to surround the vertical MOS transistor 10.
処理回路２０の部分における２１はＰウェル領域、２２
はゲート酸化膜、２３．２４．２５はそれぞれＮＭｏ５
トランジスタ１８のソース領域、ドレイン領域およびゲ
ート電極であり、また２６．２７．２８はそれぞれＰＭ
ＯＳトランジスタのソース領域、ドレイン領域およびゲ
ート電極である。In the processing circuit 20 part, 21 is a P well region, 22
is the gate oxide film, and 23, 24, and 25 are NMo5, respectively.
The source region, drain region and gate electrode of the transistor 18, and 26, 27 and 28 are PM respectively.
These are the source region, drain region, and gate electrode of the OS transistor.
そして処理回路２０からの駆動信号により縦形ＭＯ８ｔ
−ランジスタ１０のスイッチング動作等が行なわれる。Then, by the drive signal from the processing circuit 20, the vertical MO8t
- Switching operations of transistor 10, etc. are performed.
このとき処理回路２０を構成するＮＭＯＳトランジスタ
１８およびＰＭＯＳトランジスタ１９等の各素子は、接
地電位に保持されるＰ＋基板１およびＰ形ガードリング
１７でシールドされるので、縦形ＭＯＳトランジスタ１
０の動作による影響を受けることなく、適正な動作が行
なわれる。At this time, each element constituting the processing circuit 20, such as the NMOS transistor 18 and the PMOS transistor 19, is shielded by the P+ substrate 1 and the P type guard ring 17, which are held at the ground potential.
Proper operation is performed without being affected by the operation of 0.
〔発明の効果］
以上説明したように、この発明によれば、第１導電形の
基板上に第２導電形層を形成し、この第２導電形層に前
記基板に接続される第１導電形のウェル領域を形成し、
このウェル領域内に第２導電形のドレイン領域を形成し
、このトレイン領域と前記第２導電形層で形成されるソ
ース領域との間のウェル領域上にゲート絶縁膜を介して
ゲート電極を設け、前記基板の裏面には溝を穿設して前
記のソース領域および基板に接続されるソース電極を設
けたので、同一チップ上に複数個の縦形ＭＯＳトランジ
スタを形成することができる。また負荷駆動方式として
、ソース電極を接地して負荷をドレイン領域側に接続す
る負荷ドレイン側方式としたとき、基板はソース電極に
接続されて電位変動の生じることがないので、昇圧回路
等を必要とすることなく同一の基板上に縦形ＭＯＳトラ
ンジスタの制御回路を含む他の処理回路等を容易に集積
化することができるという利点がある。[Effects of the Invention] As explained above, according to the present invention, a second conductivity type layer is formed on a substrate of a first conductivity type, and a first conductivity type layer connected to the substrate is formed on the second conductivity type layer. form a shaped well area,
A drain region of a second conductivity type is formed in this well region, and a gate electrode is provided via a gate insulating film on the well region between this train region and a source region formed of the second conductivity type layer. Since a groove is formed in the back surface of the substrate and a source electrode connected to the source region and the substrate is provided, a plurality of vertical MOS transistors can be formed on the same chip. In addition, when the load drive method is a load drain side method in which the source electrode is grounded and the load is connected to the drain region side, a booster circuit etc. is required because the substrate is connected to the source electrode and no potential fluctuation occurs. There is an advantage that other processing circuits, including a control circuit for vertical MOS transistors, can be easily integrated on the same substrate without having to do so.
第１図はこの発明に係る半導体装置の一実施例を示す縦
断面図、第２図はこの発明の他の実施例を示す縦断面図
、第３図は従来の半導体装置を示す縦断面図である。
１：Ｐ＋基板、
２：Ｎ形層、
３：Ｎソース領域、
４：Ｎ＋ソース領域、
５．１５：Ｐウェル領域、
６ ： Ｐ”基板連結ｆｒＡｖｉ、
７：Ｎ＋ドレイン領域、
８：チャネル、
９：ゲート電極、
１０：縦形ＭＯＳトランジスタ、
１１：ゲート酸化！ｌ（絶縁膜）、
１３ニドレイン電極、
１４：溝、
１６：ソース電極、
２０：処理回路。
代理人 弁理士 三 好 保 男
第１ 図FIG. 1 is a longitudinal sectional view showing one embodiment of a semiconductor device according to the present invention, FIG. 2 is a longitudinal sectional view showing another embodiment of the invention, and FIG. 3 is a longitudinal sectional view showing a conventional semiconductor device. It is. 1: P+ substrate, 2: N type layer, 3: N source region, 4: N+ source region, 5.15: P well region, 6: P'' substrate connection frAvi, 7: N+ drain region, 8: channel, 9 : Gate electrode, 10: Vertical MOS transistor, 11: Gate oxidation!l (insulating film), 13 Nidrain electrode, 14: Groove, 16: Source electrode, 20: Processing circuit. Agent: Yasuo Miyoshi, Patent Attorney Figure 1
Claims (1)
電形のウェル領域と、 該ウェル領域内に形成された第２導電形のドレイン領域
と、 該ドレイン領域と前記第２導電形層で形成されるソース
領域との間の前記ウェル領域上にゲート絶縁膜を介して
設けられ当該ウェル領域にチャネルを誘起させるゲート
電極と、 前記基板の裏面に穿設された溝により前記ソース領域お
よび前記基板に接続されるソース電極とを有することを
特徴とする半導体装置。[Scope of Claims] A substrate of a first conductivity type, a second conductivity type layer formed on the substrate, and a first conductivity type well region formed on the second conductivity type layer and connected to the substrate. a drain region of a second conductivity type formed in the well region; and a drain region of a second conductivity type formed on the well region between the drain region and a source region formed of the second conductivity type layer via a gate insulating film. 1. A semiconductor device comprising: a gate electrode provided to induce a channel in the well region; and a source electrode connected to the source region and the substrate through a groove bored in the back surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61296683A JPS63150957A (en) | 1986-12-15 | 1986-12-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61296683A JPS63150957A (en) | 1986-12-15 | 1986-12-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63150957A true JPS63150957A (en) | 1988-06-23 |
Family
ID=17836727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61296683A Pending JPS63150957A (en) | 1986-12-15 | 1986-12-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63150957A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07321214A (en) * | 1994-05-19 | 1995-12-08 | Consorzio Per La Ric Sulla Microelettronica Nel Mezzogiorno | Electric power integrated circuit body structure and its preparation |
| CN107991598A (en) * | 2017-11-16 | 2018-05-04 | 长江存储科技有限责任公司 | A kind of measuring method for three-dimensional storage raceway groove conduction |
-
1986
- 1986-12-15 JP JP61296683A patent/JPS63150957A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07321214A (en) * | 1994-05-19 | 1995-12-08 | Consorzio Per La Ric Sulla Microelettronica Nel Mezzogiorno | Electric power integrated circuit body structure and its preparation |
| CN107991598A (en) * | 2017-11-16 | 2018-05-04 | 长江存储科技有限责任公司 | A kind of measuring method for three-dimensional storage raceway groove conduction |
| CN107991598B (en) * | 2017-11-16 | 2020-09-11 | 长江存储科技有限责任公司 | Method for measuring conductivity of three-dimensional memory channel |
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