JPH0456466B2 - - Google Patents

Description

Detailed Description of the Invention The present invention relates to a complementary semiconductor integrated circuit device (hereinafter referred to as a CMOS or CMIS semiconductor integrated circuit device) including an N-channel type insulated gate field effect transistor and a P-channel type insulated gate field effect transistor. (referred to as an integrated circuit device).

A semiconductor integrated circuit device with a CMOS structure consisting of a P-channel insulated gate field effect transistor (hereinafter referred to as MISFET) and an N-channel MISFET has a characteristically low power consumption and is a bipolar logic circuit. For example, TTL
(Transistor Transistor Logic) Since it has an output level that can drive a logic circuit, it is compatible with bipolar logic circuits. In addition, this semiconductor integrated circuit device is structurally relatively easy to design, so it is called a large-scale integrated circuit device (hereinafter simply referred to as LSI) or a super LSI.
(VLSI).

This type of semiconductor integrated circuit device generally has an interface on the output side of the logic circuit in order to provide a large driving capacity for capacitive loads to external circuits such as bipolar circuits. A pair of CMOS structures that make up the circuit section
The geometric structure of MISFET, such as channel width and channel length, constitutes the internal logic circuit section.
It is larger than MISFET with CMOS structure.

However, according to the study results of the present inventors, the CMOS structure of the interface circuit section with a large geometric structure has a smaller geometric structure than the CMOS structure of the internal logic circuit section with a smaller geometric structure. It has been found that a noise signal input from an output signal terminal, that is, an output signal terminal of a semiconductor integrated circuit device, tends to cause a latch-up phenomenon due to a parasitic PNPN thyristor structure. It has been discovered that this latch-up phenomenon causes a malfunction in the logic circuit or causes destruction of circuit elements due to the large current generated due to the latch-up phenomenon.

In other words, the CMOS of the output interface circuit
Generally, a P-type well is formed on one main surface side of an N-type silicon substrate, and an N-channel MISFET (Metal Insulator Semiconductor) is installed in this P-type well.
Field Effect Transistor) N ⁺ type source and drain regions are provided, while the N type silicon substrate is provided with P
P ⁺ type source and drain regions of the channel MISFET are provided, and the output of the internal circuit is commonly given to each gate of both MISFETs, and the output from each drain region is
It takes out the CMOS output and leads it to the output terminal. Therefore, there is a PNP parasitic bipolar transistor structure between the P ⁺ type active region of the P-channel MISFET, the N-type substrate, and the P-type well in which the N-channel MISFET is formed;
The N ⁺ type active region of MISFET, the P type well, and the N
An NPN parasitic bipolar transistor structure is formed between the mold substrate and the two parasitic transistors form a PPN parasitic thyristor structure. Therefore, when some abnormal voltage is applied from the output terminal of the CMOS (the output terminal of the semiconductor integrated circuit device), this is used as an electrical trigger to cause the parasitic thyristor to conduct, thereby forming a short circuit that crosses the power supply. Therefore, a large current will flow continuously. If an excessive amount of current flows due to this latch-up phenomenon, the CMOS itself will be thermally destroyed, an undesirable situation.

According to the inventor's study, the reason why this latch-up phenomenon is particularly likely to occur in the output circuit of the interface circuit is that the element size of the output interface circuit is large enough to drive external circuits such as TTL. This is thought to be because the equivalent current amplification factor (h _FE ) of both the parasitic PNP transistor and the NPN transistor forming the thyristor structure becomes large due to the high gain.
In order to prevent this latch-up phenomenon, it is conceivable to arrange the above-mentioned two MISFETs at a distance, for example, and to reduce the current amplification factor h _FE of the PNP parasitic transistor. However, as the degree of integration of LSI increases due to advances in microfabrication technology, the number of logic gates integrated as internal circuits increases.
Since the number of output circuits needs to increase accordingly, both
Placing the MISFETs apart from each other is difficult in terms of layout, and is disadvantageous in that it increases the area occupied by the output interface circuit.

Therefore, the main object of the present invention is to prevent the latch-up phenomenon in a CMOS type semiconductor integrated circuit device and maintain its normal driving function.

Another object of the present invention is to provide a structure of an output circuit of a CMOS type semiconductor integrated circuit device that allows easy layout and high integration.

The gist of the present invention for achieving these objects is to provide a complementary logic gate circuit comprising a P-channel insulated gate field effect transistor and an N-channel insulated gate field effect transistor;
An interface circuit for driving an external circuit connected to this logic gate circuit is formed on a common semiconductor substrate, and the interface circuit is connected to one of the N type insulated gate field effect transistors of a plurality of N type channels. The drain of the insulated gate field effect transistor of type channel is connected to the supply voltage,
Its source is coupled to the drain of the other N-channel insulated gate field effect transistor, its coupling terminal serves as an output terminal, and the source of the other N-channel insulated gate field effect transistor is connected to ground potential. The present invention provides a semiconductor integrated circuit device comprising an output circuit of a push-pull buffer, wherein an output high level voltage of the output circuit is lower than a power supply voltage and sufficiently satisfies a TTL output level.

Hereinafter, embodiments in which the present invention is applied to a CMOS type logic LSI will be described in detail with reference to the drawings.

1 and 2 according to embodiments of the invention
A schematic diagram of the layout of an LSI with a CMOS structure is shown. This LSI was formed to provide a certain logical function.

An IC chip 1 made of a silicon semiconductor substrate of about 12 mm square has a logic circuit section 2 formed in an area of about 10 mm square occupying the center, and a space 3 of about 120 μm from this logic circuit section (internal circuit section). A peripheral circuit section 4 for connecting the input/output terminals of the logic circuit section 2 and an external circuit is formed in an area approximately 300 μm wide surrounding the internal circuit section 2 from all sides in a state of
It consists of a row of bonding pads 5 provided on the periphery with a width of 580 μm and electrically connected to the peripheral circuit section. The logic circuit section 2 occupies about 70% of the entire chip, and consists of N-channel MISFET rows 6 and P-channel MISFET rows 7 arranged alternately, as will be described in detail later. constitutes a large-scale logic with tens of thousands of gates. This logic circuit section 2 includes NAND,
CMOS by a collection of unit circuits such as exclusive OR
It consists of The peripheral circuit section 4 includes an input interface circuit section coupled to the input side of the logic circuit section 2 for transmitting an input signal from an external circuit to the logic circuit section 2, and an input interface circuit section coupled to the output side of the logic circuit section 2. , and an output interface circuit for transmitting the output signal to other external circuits.
The input interface circuit section receives signals from outside the LSI, so it
The MISFET that forms the CMOS inverter circuit is
It can be formed with almost the same geometric dimensions as the MISFETs constituting the internal logic circuit section 2. On the other hand, since the output interface circuit section needs to drive other external circuits of the LSI, it is necessary to increase the size of the MISFET that makes up the output interface circuit section. According to the invention, this output interface circuitry has the same conductive channel, namely N
The channel MISFET constitutes an output inverter circuit (buffer circuit). This peripheral circuit section occupies, for example, 20 to 30% of the entire chip, including the area of the bonding pad 5, and takes the form of input interface circuits and output interface circuits arranged alternately. I can do it.

A region 3 between the internal circuit section 2 and the peripheral circuit section 4 is provided with a large number of aluminum wiring lines as wiring channels. The bonding pad 5 is actually electrically connected to each input/output terminal of the input interface circuit section (peripheral circuit section), and the number of corresponding pins is, for example, 200 pins.

In such an embodiment, a bonding pad for output in which the above-mentioned latch-up is a problem will be described in detail below.

The internal circuit section 2 is specifically as shown in FIG.
It has a CMOS structure. That is, on one main surface of the N-type silicon substrate, a P-type well 8 that continuously extends long and thin from the left side to the right end of the internal circuit section is formed for each row of the N-channel MISFET group 6, and within the well 8, the FET group 6 is formed. An N ⁺ type diffusion region 9 is formed as a source or drain region, and a polysilicon gate electrode 10 is connected to a P channel between each diffusion region via a gate insulating film on a silicon substrate.
It is provided in common with MISFET group 7. In this embodiment, in each row of the MISFET group 6, the diffusion regions 9 are separated, for example, every three gate electrodes 10, and therefore the N-channel MISFET group 6 has a unit configuration of four diffusion regions 9 and three gate electrodes 10.
A large number of wells 9 are arranged separately from each other along the length direction of the well 9. On the other hand, P channel
The MISFET group 7 is arranged in the same way, and in each row there are four as source or drain regions corresponding to the units of the N-channel MISFET group 6.
P ⁺ -type diffusion region 11 and three polysilicon gate electrodes 10 form one unit. In addition,
Aluminum wiring for forming NAND gates and the like in these FET groups 6 and 7 is not shown. For example, _the P channel MISFETT _{1 -} T ₂ formed in FIG. by an aluminum trace (not shown) extending over the
A NAND gate circuit as shown in the figure can be formed.

The peripheral circuit section 4 according to the present invention includes a pair of N-channel MISFETs 12 shown in FIGS. 4 and 5.
and 13 are formed as a unit structure. These pair of MISFETs form the above-mentioned output interface circuit, and are the internal circuit 2 of the LSI.
It is placed between the CMOS of the LSI and an external circuit such as a TTL connected to the outside of the LSI, and is used to convert these levels. Each MISFET 12 and 13 is provided in a P-type well 15 formed on one main surface of an N-type silicon substrate 14, and includes an N ⁺ type source region 16 and a drain region 17, which are all of the same conductivity type.
It has a source region 18 and a drain region 19, respectively. And each input from the internal circuit mentioned above
IN _A and IN _B are aluminum wiring 20 and 21, respectively.
between each diffusion region 16 and 17, 18 and 1
Polysilicon gate electrodes 22, 23 extending between 9
given to. Further, each drain region 17 of one FET group 12 is applied with a power supply voltage V _DD through an aluminum wiring 24, and each source region 18 of the other FET 13 is applied with a ground potential through an aluminum wiring 25. This allows a pair of
FETs 12 and 13 form a push-pull inverter circuit. The output of this inverter circuit is transmitted from each source region 16 and drain region 19 of a pair of FETs 12 and 13 to an aluminum wiring 26.
extracted by. The size per unit of this interface circuit is, for example, 300μm x 100μm.
m, and a large number of units of this are arranged around the internal circuit as shown in FIG. In FIG. 4, the contact regions between each of the aluminum wires 24 to 26 and each diffusion region, and the contact regions between each of the aluminum wires 20 and 21 and the gate electrodes 22 and 23 are indicated by cross marks, respectively. Further, in FIG. 5, 27 is a field SiO ₂ film for element isolation, 28 is a gate oxide film, 29 is an SiO ₂ film on the surface of the polysilicon gate electrode, and 30 is a phosphosilicate glass film.

Next, the electrical connection relationship between the internal circuit and the interface circuit configured as described above and the electrical connection relationship with the external TTL circuit will be explained with reference to FIG.

As shown in Figure 6, the internal circuit is actually
It consists of an MIS type logic gate with a CMOS inverter structure, and the output of the inverter at the output stage is applied to the gate of MISFET 12 of the interface circuit, and the input to the inverter is also applied to the gate of MISFET 13 of the interface circuit. be done. MISFETs 31, 32 and 33 in the internal circuit are of the P channel enhancement type, and MISFETs 34, 35 and 36 are of the N channel enhancement type. Also,
The interface circuit composed of MISFETs 12 and 13 functions as a push pull buffer with external TTL drive capability, and for this reason, its output is transmitted via the bonding wire connected to the output terminal consisting of the pad 5 mentioned above. and is input to the TTL circuit. In this interface circuit, the high level of the output is lower than the power supply voltage V _DD by the threshold voltage of the MISFET, but it is sufficient as a TTL level, and the interface conditions are fully satisfied. .

What should be noted here is that the interface circuit is entirely composed of N-channel MISFETs 12 and 13. Therefore, as shown structurally in Figure 5, the CMOS structure is fundamentally different from the CMOS structure described above and causes latch-up.
There will be no PNPN thyristor structure. Therefore, even if some kind of electrical trigger is applied to the interface circuit via the bonding pad 5, it is possible to effectively prevent element destruction due to latch-up. This is extremely significant, especially for the normal operation of interface circuits that tend to pick up external noise. Moreover, unlike the previously mentioned CMOS structure, there is no need to separate the elements to prevent latch-up, so the interface circuit itself can be made into finer patterns, which can accommodate the number of internal logic gates. Highly integrated output circuits can be formed.

Note that the internal circuit described above is made of CMOS, but the latch-up phenomenon is less likely to occur there. That is, since the element size of the CMOS in the internal circuit is extremely small compared to the elements in the output circuit, the current amplification factor h _FE of the parasitic NPN and PNP bipolar transistors becomes equivalently small.
For example, the area occupied by each element in the internal circuit is less than 1/100 of the area per element in the peripheral circuit, and the equivalent h _FE becomes extremely small.

Furthermore, although this embodiment has described prevention of latch-up in the interface circuit of the output circuit section, it should be added that such latch-up phenomenon does not pose a problem in the input interface circuit. That is, in the input interface circuit, as shown in the equivalent circuit of FIG. 8, an input protection resistor ( R _P )
is connected to a protection diode (Z _P ) formed in the semiconductor substrate, but even if pulse-like noise enters from the input terminal, this will be caused by the resistance R _P of the protection resistor and the capacitance C of the protection diode Z _P , or is clamped by the protection diode Z _P , so that a sufficient signal is not input as a trigger signal for the thyristor structure. Also, even if noise enters through the gate without being attenuated, the input interface circuit
Due to the small size of CMOS MISFETs T ₇ and T ₈ , the h _FE of the parasitic PNP or NPN transistors is small, so that latch-up as described above cannot occur.

As is clear from the above description of the embodiments, the present invention
This was developed by focusing on the fact that the latch-up phenomenon is particularly likely to occur due to the thyristor structure in output buffers (output interface circuits) with a CMOS structure, and the output buffer circuit is formed by multiple MISFETs in a single channel. It is characterized by According to the present invention, a pair of identical conductive channels constituting an output buffer circuit
Even if the MISFET is formed into large geometric dimensions,
This will not cause thyristor generation. For example, a pair of channel MISFETs of the same conductivity type is formed with an area that occupies more than 50 times the area occupied by a pair of CMOS-structured MISFETs in the internal logic circuit, thereby improving the driving ability for external circuits. can be done.

Although the present invention has been illustrated above, the above-described examples can be further modified based on the technical idea of the present invention.
For example, if the interface circuit described above is
Can be configured with only MISFET. In this case, convert the polarity of the power supply and
N-channel MISFET in CMOS inverter
It is necessary to connect the P-channel MISFET to the power supply side and the P-channel MISFET to the ground side. Suppose that the interface circuit is simply converted into a P channel with the connection shown in Figure 6.
When configured with a MISFET, it becomes a source follower, so a threshold voltage can be obtained as the output voltage especially when the FET is conductive, but this output voltage does not reach the ground level (“0”) and drives the TTL in the next stage. Since the level is higher than that, level conversion becomes impossible. In this sense, when connecting as shown in FIG. 6, level conversion with TTL is only possible if the FET of the interface circuit is an N-channel type. Also, in the structure shown in Figure 3, CMOS
Although a P-type well is formed for the purpose of the present invention, instead of this, an N-type well may be formed to provide a P-channel MISFET, and an N-channel MISFET may be provided on the P-type substrate. In this case, since the board is P type, the N channel of the above interface circuit
MISFET does not need to be provided in a P-type well as shown in FIG. 5, and an N ⁺ type diffusion region can be formed directly on the substrate itself, eliminating the need for isolation means such as a well. It should be noted that the present invention is not limited to the circuit configuration described above, and can of course be applied to various logic circuits, and the external circuit is only exemplified in the above example.

As described above, in the present invention, the interface circuits connected to the complementary internal circuits are all composed of insulated gate field effect transistors of the same conductivity type channel, thereby eliminating the parasitic thyristor structure and preventing latch-up caused by noise. It is possible to prevent this and ensure normal interface function. Moreover, even if the circuit elements constituting the interface circuit are formed into fine patterns, no latch-up occurs, so that a highly integrated output circuit can be easily laid out.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, in which FIG. 1 is a plan view schematically showing the entire layout of a logic LSI, FIG. 2 is a partially enlarged plan view of FIG. 1, and FIG. FIG. 4 is a partially enlarged plan view of the internal logic gate of the LSI shown in FIG. 1, and FIG. 4 is a partially enlarged plan view of the interface circuit section on the output side of the LSI shown in FIG.
Figure 5 is a cross-sectional view taken along line X-X in Figure 4, Figure 6 is an equivalent circuit diagram between the internal circuit, interface circuit and TTL circuit, and Figures 7 and 8 are shown in Figure 1. FIG. 2 is an equivalent circuit diagram of a part of the LSI. In addition, in the symbols used in the drawings, 2
is the internal circuit section, 4 is the peripheral circuit section, 5 is the bonding pad, 6 is the N-channel MISFET group, and 7 is the P
Channel MISFET group, 8 and 15 are P-type wells,
12 and 13 are N channels of the interface circuit.
In the MISFET group, 20, 21 and 24 to 26 are aluminum wiring lines, and 22 and 23 are polysilicon gate electrodes.

Claims (1)

[Claims] 1 a complementary logic gate circuit consisting of a P-type channel insulated gate field effect transistor and an N-type channel insulated gate field effect transistor;
An interface circuit for driving an external circuit connected to this logic gate circuit is formed on a common semiconductor substrate, and the interface circuit is connected to one of the N type insulated gate field effect transistors of a plurality of N type channels. The drain of the insulated gate field effect transistor of type channel is connected to the supply voltage,
Its source is coupled to the drain of the other N-channel insulated gate field effect transistor, its coupling terminal serves as an output terminal, and the source of the other N-channel insulated gate field effect transistor is connected to ground potential. 1. A semiconductor integrated circuit device comprising an output circuit of a push-pull buffer, wherein an output high level voltage of the output circuit is lower than a power supply voltage and sufficiently satisfies a TTL output level.