JPS54153582A - Manufacture for semiconductor device - Google Patents
Manufacture for semiconductor deviceInfo
- Publication number
- JPS54153582A JPS54153582A JP6161278A JP6161278A JPS54153582A JP S54153582 A JPS54153582 A JP S54153582A JP 6161278 A JP6161278 A JP 6161278A JP 6161278 A JP6161278 A JP 6161278A JP S54153582 A JPS54153582 A JP S54153582A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resist
- exposed
- sio
- sin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Element Separation (AREA)
Abstract
PURPOSE: To establish the semiconductor device in which the inversion of the part along the semiconductor element boundary is avoided and the reduction in the effective semiconductor element width is less.
CONSTITUTION: On the transmissive substrate 3, the P type single crystal Si layer 4, buffer SiO2 layer 5, SiN layer 6, and buffer SiO2 layer 7 are formed in lamination, and the resist is coated and the mask 8 is formed on the SiO2 layer 7 (Fig. a). Further, the SiO2 layer 7, SiN layer 6 and SiO2 layer 5 are respectively etched and a part of the Si layer 4 is exposed (Fig. b). After etching the Si layer 4, the exposed Si layer 4 is thermally oxided to grow the field oxide insulation layer 9 (Fig. c). Further, the SiN layer 6 is removed (Fig. d) and the positive type resist 10 is coated on the surface of the Si layer 4 and the insulation layer 9 (Fig. e). The resist 10 is exposed from the lower side of the substrate 3. In this case, only the resist 10 on the insulation layer 9 is exposed. Further, the exposed resist 10 is removed (Fig. f) and the P type impurity is injected from the upper side, allowing to inject the P type impurity on the insulation layer 9 not covered with the resist 10 and the Si layer 4 around it.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53061612A JPS5816619B2 (en) | 1978-05-25 | 1978-05-25 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53061612A JPS5816619B2 (en) | 1978-05-25 | 1978-05-25 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54153582A true JPS54153582A (en) | 1979-12-03 |
JPS5816619B2 JPS5816619B2 (en) | 1983-04-01 |
Family
ID=13176155
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53061612A Expired JPS5816619B2 (en) | 1978-05-25 | 1978-05-25 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5816619B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57196579A (en) * | 1981-05-28 | 1982-12-02 | Nec Corp | Sos/mos transistor and manufacture thereof |
-
1978
- 1978-05-25 JP JP53061612A patent/JPS5816619B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57196579A (en) * | 1981-05-28 | 1982-12-02 | Nec Corp | Sos/mos transistor and manufacture thereof |
JPH0514430B2 (en) * | 1981-05-28 | 1993-02-25 | Nippon Electric Co |
Also Published As
Publication number | Publication date |
---|---|
JPS5816619B2 (en) | 1983-04-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS54153582A (en) | Manufacture for semiconductor device | |
JPS56140641A (en) | Manufacture of semiconductor device | |
JPS57111042A (en) | Manufacture of semiconductor device | |
JPS54153583A (en) | Semiconductor device | |
JPS56103443A (en) | Production of element isolation structure for semiconductor device | |
JPS52130575A (en) | Semiconductor device and its preparation | |
JPS5735368A (en) | Manufacture of semiconductor device | |
JPS54114079A (en) | Mesa-type semiconductor device | |
JPS5633841A (en) | Manufacture of semiconductor device | |
JPS5580319A (en) | Manufacture of semiconductor device | |
JPS5679446A (en) | Production of semiconductor device | |
JPS54117690A (en) | Production of semiconductor device | |
JPS5572052A (en) | Preparation of semiconductor device | |
JPS56133844A (en) | Semiconductor device | |
EP0067738A3 (en) | Method of reducing encroachment in a semiconductor device | |
JPS5577134A (en) | Formation of fine pattern | |
JPS6430244A (en) | Manufacture of semiconductor device | |
JPS5575233A (en) | Manufacturing semiconductor integrated circuit | |
JPS5567140A (en) | Method for manufacturing semiconductor device | |
JPS5478668A (en) | Manufacture of semiconductor device | |
JPS54116185A (en) | Manufacture for semiconductor device | |
JPS5463674A (en) | Production of mesa-type semiconductor device | |
JPS57106048A (en) | Manufacture of semiconductor device | |
JPS5762542A (en) | Manufacture of semiconductor device | |
JPS52135675A (en) | Anisotropic ethcing of semiconductor single crystal |