JPS54114079A - Mesa-type semiconductor device - Google Patents

Mesa-type semiconductor device

Info

Publication number
JPS54114079A
JPS54114079A JP2110778A JP2110778A JPS54114079A JP S54114079 A JPS54114079 A JP S54114079A JP 2110778 A JP2110778 A JP 2110778A JP 2110778 A JP2110778 A JP 2110778A JP S54114079 A JPS54114079 A JP S54114079A
Authority
JP
Japan
Prior art keywords
region
mesa
layer
resist
trapezoid part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2110778A
Other languages
Japanese (ja)
Inventor
Saburo Takamiya
Osamu Ishihara
Yasuro Mitsui
Masaaki Nakatani
Shigeru Mitsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2110778A priority Critical patent/JPS54114079A/en
Publication of JPS54114079A publication Critical patent/JPS54114079A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To secure a height difference of ±0.5μm between the trapezoid part coated with the insulator film and the area except for the trapezoid part and thus to facilitate the formation of the micropattern electrode on the trapezoid part for the mesa-type semiconductor device which uses the trapezoid part of the semiconduc tor layer as the active region.
CONSTITUTION: Buffer layer 2 and active layer 3 are formed in lamination on semiconductor substrate 1, and the mesa-like region of layer 3 is covered with photo resist 8. Then the selective etching is applied using resist 8 as the mask to make only necessary region 3 remain and to remove other regions, and the entire surface is covered with insulator film 6 made of glass, SiO, SiO2, Si3N4 and the like. After this, resist 8 and film 6 coated on 8 are removed together to expose region 3. In this case, a height difference of ±0.5μm between region 3 and mesa edge part 7 at the boundary between region 3 and its surrounding film 6. As a result, no disconnection is caused to the wiring formed on the gate finger even through the gate finger features a small width.
COPYRIGHT: (C)1979,JPO&Japio
JP2110778A 1978-02-24 1978-02-24 Mesa-type semiconductor device Pending JPS54114079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2110778A JPS54114079A (en) 1978-02-24 1978-02-24 Mesa-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2110778A JPS54114079A (en) 1978-02-24 1978-02-24 Mesa-type semiconductor device

Publications (1)

Publication Number Publication Date
JPS54114079A true JPS54114079A (en) 1979-09-05

Family

ID=12045644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2110778A Pending JPS54114079A (en) 1978-02-24 1978-02-24 Mesa-type semiconductor device

Country Status (1)

Country Link
JP (1) JPS54114079A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59138086A (en) * 1983-01-25 1984-08-08 シャープ株式会社 Substrate connecting method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59138086A (en) * 1983-01-25 1984-08-08 シャープ株式会社 Substrate connecting method
JPH0151033B2 (en) * 1983-01-25 1989-11-01 Sharp Kk

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