JP3231311B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device,
The present invention relates to a bipolar transistor in which an element isolation structure is improved by trench isolation.

[Conventional technology]

As one of the element isolation structures of a semiconductor integrated circuit device, a groove is dug in a main surface of a semiconductor substrate so as to surround an active region where an active element such as a bipolar transistor or a MOSFET is to be formed, and polysilicon is filled in the groove. A groove isolation structure to be filled is described in, for example, “Nikkei Electronics” published on March 29, 1982 (pages 94 to 95).

As a manufacturing method of the above-described conventional groove isolation structure, for example, a groove is formed by etching a main surface of a semiconductor substrate made of silicon, and a silicon oxide film is formed by oxidizing a silicon surface in the groove. Then, after thickly depositing polysilicon on the entire surface of the semiconductor substrate including the inside of the trench, the polysilicon is buried in the trench formed on the main surface of the semiconductor substrate by etching back the polysilicon. are doing.

[Problems to be solved by the invention]

However, when the method of embedding the polysilicon in the trench as in the above-described prior art is adopted, the dielectric constant in the trench becomes a large value (up to 11) due to the filled polysilicon, and the gap between the isolation region and the active element is formed. The parasitic capacitance to be formed and the parasitic capacitance formed between the isolation region and the wiring are increased, which hinders the high-speed operation of the LSI.

In order to prevent the above-mentioned increase in the dielectric constant, a low dielectric constant (3-4) is used instead of polysilicon (Chemical Vaper Deposit).
It is conceivable to fill the trench with an insulating film formed by ion (CVD).

When the trench is buried with the above-mentioned CVD insulating film, theoretically, if the CVD insulating film having a width of 1/2 or more of the groove to be buried is deposited on the semiconductor substrate, the groove is completely filled with the CVD insulating film. Will be able to

However, the bonding property (adhesion) between the CVD insulating films is weaker than that of the polysilicon, and as in the case of embedding the polysilicon described above, once the CVD insulating film is deposited,
When the etch-back is performed, the bonding interface of the CVD insulating film deposited on both side surfaces of the groove is exposed, and only the center of the groove progresses easily along the interface, so that the groove can be buried flat. A process failure that cannot be performed occurs.

On the other hand, it is conceivable that the CVD insulating film deposited on the semiconductor substrate is left as it is without being etched back so as not to expose the bonding interface between the CVD insulating films in the groove. However, for example, the insulating film is considerably thick on the semiconductor substrate in the active element formation region.

However, if the CVD insulating film is deposited thick as described above, there is a problem that the time required for the deposition becomes long. As described above, if the CVD insulating film is left thick on the semiconductor substrate, formation of a diffusion layer as an active region to be formed later on the main surface of the semiconductor substrate and wiring to be formed on the CVD insulating film It is difficult to form a contact between the layer and a diffusion layer formed on the main surface of the semiconductor substrate.

Incidentally, techniques relating to the formation of grooves for element isolation are disclosed in, for example, JP-A-58-32430, JP-A-58-132946, and JP-A-61-5.
No. 1937 and Japanese Patent Application Laid-Open No. 63-232461, but there is no description regarding optimization of the shape of the CVD insulating film formed in the groove.

SUMMARY OF THE INVENTION The present invention has been made in view of the circumstances, and enables a groove isolation structure having a low dielectric constant and high reliability, thereby improving the integration degree and further simplifying the manufacturing process. It is a main object to provide a method for manufacturing a semiconductor integrated circuit device.

The objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows.

That is, a method of manufacturing a semiconductor integrated circuit device includes the following steps.

(A) a step of forming a first shallow groove by selectively etching a main surface of a semiconductor substrate, wherein the first shallow groove is formed so as to surround an active region where an active element is to be formed; (B) forming a second deep groove by selectively etching a part of the bottom surface of the first shallow groove;
A width of the second groove is smaller than a width of the first groove; (c) depositing an insulator by a CVD method on a main surface of the semiconductor substrate including on the first and second grooves; Forming an insulating film in the first and second trenches and on the active region; (d) etching back the insulating film by anisotropic etching to remove the insulating film on the active region; Leaving the insulating film in the first and second grooves.

(Operation)

According to the above-described means (manufacturing method), since the second deep groove which is actually an isolation groove is formed at the bottom surface of the first shallow groove, the second deep groove is formed at the time of etching back the insulating film. Since the bonding (junction) interface of the insulating film formed substantially at the center of the deep groove is not exposed, the insulating film can be buried flat in the first deep groove. Also,
Since the region where the active element is to be formed is formed so as to protrude from the bottom surface of the first shallow groove by forming the first shallow groove, the insulating film does not remain thickly on the active region. Therefore, it is not difficult to form a diffusion layer formed on the active region or a contact for connecting the diffusion layer to the wiring layer, and it is possible to improve the reliability of the semiconductor integrated circuit device. is there.

〔Example〕

Hereinafter, a method for manufacturing a semiconductor integrated circuit device to which the present invention is applied will be described with reference to the drawings.

1 to 17 are main-portion cross-sectional views for explaining a manufacturing process of the semiconductor integrated circuit device of the present embodiment.

 Hereinafter, the manufacturing process will be specifically described.

First, as shown in FIG. 1, a semiconductor gas 1 composed of an epitaxial layer 1a made of N ⁻ type single crystal silicon, an N ⁺ buried layer 1b and a semiconductor substrate 1c made of P ⁻ type single crystal silicon is prepared. An oxide film 2 is formed on the main surface of 1a, and a photoresist film 3 covering an element formation region where an active element is to be formed is selectively formed.

Next, as shown in FIG.
Is used as an etching mask to etch and pattern oxide film 2. Thereafter, after the photoresist film 3 is removed, the semiconductor gas 1 (N ⁻ -type epitaxial layer 1a) is etched using the patterned oxide film 2 as an etching mask to form a first shallow layer serving as an isolation region. The grooves 1Fa and 1Fb are formed.

Next, as shown in FIG. 3, the oxide film 2 is removed, and an insulator, for example, silicon oxide is deposited on the semiconductor substrate 1 including the first shallow trenches 1Fa and 1Fb by a CVD method. Membrane 4
Is formed.

Next, as shown in FIG. 4, a photoresist film 5 is formed on the insulating film 4, and an opening OP1 is formed by photolithography and an etching technique. The width of the opening OP1 is processed to, for example, 1.0 μm, which is the minimum processing dimension of the photolithography used in the present embodiment. Next, using the photoresist film 5 as an etching mask, the insulating film 4 is used.
Is selectively etched, and the insulating film 2 has a width of 1.0 μm.
An opening 4a of about m is formed.

Next, after the photoresist 5 is removed, as shown in FIG. 5, the thickness of the opening 4a is reduced to less than half of the width (1.0 μm), for example, about 0.3 μm on the insulating film 4 including the opening 4a. Then, an insulating film 6 made of a silicon oxide film is formed by a CVD method.

Next, as shown in FIG. 6, the substrate 1 is subjected to anisotropic etching in the vertical direction on the insulating film 6, and a sidewall spacer 6a made of the insulating film 6 is formed on the side wall of the insulating film 4 in the opening 4a. An opening 7 having a substantial width of 0.5 μm or less is formed. Thus, the side wall spacers
Forming a finer pattern than photolithography is called side film processing.

Next, as shown in FIG. 7, using the sidewall spacers 6a and the insulating film 4 as an etching mask, the gas 1 exposed from the openings 7 is etched to a desired depth by anisotropic etching to form the semiconductor substrate 1C. To obtain a second deep trench 8 having a submicron width. Thereafter, a p-type impurity, for example, boron is introduced into the bottom portion 9 of the second deep groove 8 to form a stopper region 9a. The p-type impurity is introduced by, for example, an ion implantation method.

Next, as shown in FIG. 8, the CVD insulating films 4, 6a are completely removed by, for example, wet etching.

Next, as shown in FIG. 9, the first shallow groove 1F is formed on the entire surface of the silicon gas 1 in which the second deep groove 8 is formed.
Insulator (CVD oxide film 12) with thickness approximately the same as a, 1Fb depth
Is deposited. In this embodiment, before forming the insulating film 12, first, a silicon oxide film 10 as a base is formed on the surface of the silicon substrate 1 by a thermal oxidation method, and the oxidation resistance and stress resistance of the semiconductor gas 1 are further checked. To ensure this, a silicon nitride film 11 is formed on the oxide film 10 by, for example, a CVD method.

Next, as shown in FIG. 10, a resist film (organic film) 13 for planarization is formed so as to cover the oxide film 12, and the first
The step caused by the shallow grooves 1Fa and 1Fb is almost eliminated.

Next, as shown in FIG. 11, a resist film 13, an oxide film 12,
The oxide film 10 and the silicon nitride film 11 are sequentially etched back by anisotropic etching until the silicon gas 1 is exposed, and the insulating film 12 is buried in the second deep groove 8 and the first shallow grooves 1Fa and 1Fb. I do. Although the silicon of the base 1 is used for detecting the end point of the etch back, the silicon nitride film 11 may be used as an end point detection (etching stopper).

Incidentally, in FIG. 11, 1S ₁ and 1S ₂ are actually shows the main surface of the active region where the active element is formed. Thus, the second deep groove 8 and the first shallow grooves 1Fa, 1Fb
By burying the insulating film 12 in the same manner, the insulating film 12 can be buried flat in the second deep groove which actually reaches the semiconductor substrate 1C and becomes the isolation groove. It should be noted here that the surface of the second deep groove 8 (specifically, the bottom surface of the first shallow groove 1Fa) is not exposed when the insulating film 12 is etched back and planarized. This solves the problem that the junction interface (coupling sea surface) between CVD insulating films is not exposed as in the prior art described above, so that etching proceeds along the sea surface and planarization becomes difficult. it can.

Next, the active regions 1S ₁ and 1S ₂ formed so as to be surrounded by the flattened isolation structure described in FIG. 11 with reference to FIGS. 12 to 17 should be formed. A method for manufacturing a bipolar transistor as an active element will be described.

Here, although not shown, after the step of FIG.
The S _2, a high concentration n-type impurity, e.g., phosphorus (p) is introduced, the collector lead-out region to reach the N ⁺ -type buried layer 1b is formed. Further, the active region 1S ₁ emitter region of said bipolar transistor (actually N ^- epitaxial layer 1a) the base region and the intrinsic collector region is a region to be are formed. 12 17 FIGS., The active region 1S ₁ shows only mainly emitter region, and illustrating a step of forming a base region, not shown for the active region 1S ₂ collector extraction region is formed I do.

First, as shown in FIG. 12, oxide film on the surface of the active region 1S ₁ to form a (SiO ₂ film) 36, and then depositing a silicon nitride film 37 on the oxide film 36, further the silicon nitride film 37 Non-doped polysilicon 38 is formed on the surface by, for example, a CVD method, and a silicon oxide film 39 and a silicon nitride film 40 are sequentially formed on the upper surface. Next, a photoresist mask 41 is formed by ordinary photolithography and etching techniques.
Is used as a mask to selectively etch the silicon nitride film 40 therebelow, and thereafter, using the photoresist mask 41 as a mask for introducing impurities, a p-type impurity, for example, boron (B) is ion-implanted into the non-doped polysilicon 38. The state completed so far is shown in FIG.

Thereafter, the photoresist 41 is removed, and the introduced p-type impurity is annealed as shown in FIG. As a result, the outer portion of the silicon nitride gap 40 becomes boron-doped silicon 38a (the reference numeral 38a is used to distinguish it from the non-doped polysilicon 38), while the non-doped polysilicon 38 remains below the silicon nitride film. Will be. Next, using the silicon nitride film 40 as a mask, the oxide film 39 is wet-etched with, for example, an HF-based etchant. At this time, as shown in FIG.
The oxide film 39 under the silicon nitride film 40 is side-etched.

Next, after removing the silicon nitride film 40 serving as a mask, as shown in FIG. 14, the remaining oxide film located on the lower side
By performing selective etching of non-doped polysilicon 38 with hydrazine using 39 as an etching mask,
A portion of the silicon nitride film 37 below the etched non-doped polysilicon 38 is partially exposed.

Thereafter, after removing the oxide film 39 as a mask used for the selective etching, as shown in FIG. 15, a non-doped polysilicon 38 and a boron-doped polysilicon 38a are formed.
After etching the exposed nitride film 37 using the etching mask as a mask, the non-doped polysilicon
Then, using the silicon nitride film 37 as a mask for introducing impurities, a p-type impurity for forming an external base region of the bipolar transistor, for example, boron (B) is formed on the main surface of the N ⁻ epitaxial layer 1a. Ion implantation. Next, the silicon oxide film 37 exposed from the silicon nitride film 37 is removed by wet etching to expose the surface of the N ^- epitaxial layer 1a.

Next, as shown in FIG. 16, non-doped polysilicon is deposited on the gas 1 including the silicon nitride film 37 and annealed. Then, boron doped polysilicon
Diffusion (upwelling) of the p-type impurity (boron) implanted into 38a and the external base region occurs, and the non-doped polysilicon is changed to boron-doped polysilicon 43a except on the silicon nitride film 37. At this time, the external base area GB is also formed. Then, non-doped polysilicon remaining on the silicon nitride film 37 is selectively etched using hydrazine or the like, and boron-doped polysilicon 38a, 43
A base extraction electrode 34 made of a is formed.

Thereafter, boron-doped polysilicon 43 is formed by thermal oxidation.
After oxidizing the surface of a to form an oxide film 44, the nitride film 37 inside the emitter opening EO is used as an etching mask.
And oxide film 36 are removed by etching.

Next, as shown in FIG. 17, polysilicon is formed as an emitter extraction electrode 35 so as to make contact with the surface of the N ⁻ type epitaxial layer 1a exposed by the emitter opening EO. The intrinsic base region IB and the emitter region E are formed by successively introducing type and N-type impurities and thermally diffusing them. in this way,
An NPN bipolar transistor having an n-type emitter region E, a p-type intrinsic base region IB and an intrinsic collector region (N ⁻ -type epitaxial layer 1a) as a main operation region is almost completed.

Next, the specific operation and effect of the isolation structure in which the width of the isolation groove of the present invention described in FIGS. 1 to 11 is set to 0.5 μm or less and the groove is buried by a CVD insulating film will be described. . Hereinafter, the isolation groove according to the present invention is referred to as a U groove.

First, since the groove width of the U groove according to the present invention is 0.5 μm or less, the thickness of the CVD insulating film required for embedding the U groove can be small. That is, in the conventional method of embedding a CVD insulating film in a U-groove having a groove width of, for example, 1 μm, it is necessary to deposit a CVD insulating film as thick as, for example, about 3 μm because a depression occurs. At the time of embedding, almost no dent is formed unlike the prior art, so that flattening can be achieved even if the deposited film pressure is small. Further, since the CVD insulating film is thin, the time required for deposition is greatly reduced.

Here, matters examined by the inventors of the present invention regarding the relationship between the flatness d indicating the degree of depression of the depression formed on the U groove and the groove width W of the U groove will be described below.

FIG. 18 is a view in which a CVD insulating film having a film thickness D is deposited in a U-shaped groove having a groove width W. Assuming that an angle at which a straight line L connecting the deepest portion K of the concave portion G of the CVD insulating film formed on the U-groove and the groove shoulder M becomes a perpendicular N is α, the flatness d (the depth from the flat surface of the insulating film to the deep portion) The distance to K) is expressed by the following equation (1).

Also, Then, this is substituted into equation (1), and the following (2)
Get the expression.

Therefore, it can be seen that the flatness d changes with the square of the groove width W, and when the groove width W is made finer, the flatness is sharply improved. Suppose a submicron U groove (groove width W = 0.2μ)
Considering the case where a CVD insulating film is deposited to a thickness of 1.0 μm in m), the flatness d is 0.005 μm from the above equation (2).

Second, as shown in FIG. 19, the U-groove according to the present invention does not require the etch back of the buried insulating film, or the amount of the etch back is small and sufficient so that the bonding between the buried CVD insulating films is performed. Since there is no risk that the interface (bonding interface) I, Face is exposed, it is possible to prevent over-etching failure along the interface I, Face, and to actively reduce the cavity SP formed in the U-groove to reduce stress. Can be used

Third, in a semiconductor integrated circuit device (bipolar transistor) having a shallow groove in the silicon gas 1 as in the present embodiment, the insulator of the shallow groove and the deep U groove can be filled at the same time. Is simplified.

When the process is simplified in this way, the uniformity of the isolation film thickness within the wafer is increased.

More specifically, in the conventional trench isolation using polysilicon, the variation in the deposited film pressure of polysilicon is 5%, and the variation in etch back is 5%. 4μ thickness
m, the etch back amount is 3 μm, Error will occur. On the other hand, in the U-groove isolation according to the present invention, the CVD insulating film (1 μm)
The uniformity within the wafer is much better than the conventional one only by the error due to the variation during the formation being 0.05 μm.

Further, as a result of the study by the present inventors, it has been found that when the U-groove is formed on the silicon substrate so as to surround the active region, the groove width CW of the corner portion of the planar pattern of the U-groove is increased. That is, as shown in FIG. 20, the expansion of the groove width CW at the corner portion depends on the bending angle θ, and the groove width expansion rate Y indicating the degree is expressed as follows using the bending angle θ as a parameter ( The greater Y is, the greater the effect of expanding the groove width is.)

Here, X is the groove width before performing the above-described side film processing, a is the thickness of the side wall spacer 6a formed by the above described side film processing, and (X-2a) is the submicron after miniaturization. It corresponds to the groove width W of the U groove.

As is clear from the above equation (3), the smaller the bending angle θ of the corner, the smaller the effect of expanding the groove width.

Therefore, in the present embodiment, the layout of the U-groove processing photoresist is set to an 8-or rectangular loop isolation pattern having a small bending angle θ in order to prevent the deterioration of the flatness at the time of embedding the U-groove due to the effect of increasing the groove width.

FIG. 21 shows a layout plan view of the U-groove pattern of the octagonal loop pattern. The bending angles θ at the corners of the U-groove pattern 20 are all 45 °, and the effect of increasing the groove width at all the corners is reduced uniformly. Let me.

Regarding the effect of enlarging the groove width at the intersection of the T-shape of the U-groove pattern photomask, the effect of enlarging the groove width can be reduced by forming a pattern as shown in FIG.

FIG. 23 is a sectional view showing another embodiment for performing isolation according to the present invention on a silicon substrate without a shallow groove. In this case, the concave portions 23 and 24 on the U-groove are negligibly small (the flatness d is 1 μm when the insulating film 12 is 1 μm and the groove width is 0.2 μm).
Is 0.05 μm from the above equation (2)), so that an etch-back step for thinning is almost unnecessary.

FIGS. 24 and 25 show an SOI comprising a U-groove isolation according to the present invention comprising a silicon substrate, an oxide film and a silicon substrate.
(Silicon On Insulator) This shows an embodiment applied to a substrate, and exactly the same effects as those of the embodiments shown in FIGS. 1 to 11 and 23 can be obtained.
As described above, the isolation according to the present invention uses an SOI substrate or SOS (Silicon on Sapphire), which complicates the manufacturing process.
This is particularly effective for a semiconductor integrated circuit using a substrate.

In FIGS. 24 and 25, reference numeral 25 denotes an oxide film, and reference numeral 26 denotes a silicon substrate.

In this embodiment, the side wall spacer is formed on the wall surface of the U-groove pattern having a groove width of 1 μm to make the U-groove pattern submicron. However, the present invention is not limited to this. An oxide film is deposited, non-doped polysilicon is deposited thereon, and then boron is implanted into the non-doped polysilicon using a U-groove pattern having a groove width of 1 μm as a mask. And then etching the non-doped polysilicon portion to form a submicron U-groove pattern.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor.

〔The invention's effect〕

The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.

That is, according to the method for manufacturing a semiconductor integrated circuit device of the present invention, the separation between the corner elements of the semiconductor integrated circuit is performed by the U-groove having a groove width of 0.5 μm or less, and the U-groove is filled with an insulator. Further, the dielectric constant of the isolation of the semiconductor integrated circuit can be reduced to reduce the capacitance, and the element separation distance can be reduced to achieve the miniaturization and high integration of the integrated circuit.

Further, when the U-groove is buried by depositing a CVD insulating film, flattening is performed with a thin CVD insulating film, thereby simplifying the manufacturing process. Also, when the present invention is applied to a self-aligned double polysilicon structure bipolar transistor having a shallow groove, a U groove is formed in the shallow groove, and the shallow groove and the U groove are simultaneously filled. It is possible,
Further simplification of the manufacturing process is achieved.

[Brief description of the drawings]

1 to 11 are cross-sectional views for explaining an element isolation step of a semiconductor integrated circuit device according to the present invention. FIGS. 12 to 17 are elements formed by the steps of FIGS. 1 to 11. Sectional view for explaining a manufacturing process for forming a bipolar transistor in an active region of a semiconductor integrated circuit device having an isolation region. FIG. 18 shows groove width W of U-groove and device surface based on a study by the present inventors. FIG. 19 is a cross-sectional view for explaining a state in which an insulator is deposited in a submicron U-shaped groove according to the present invention. FIG. FIG. 21 is a plan view for explaining the relationship between the bending angle θ of the corner portion of the U-groove pattern and the groove width enlarging effect based on the examination of the user. FIG. 21 is a plan view showing a submicron U-groove pattern photomask according to the present invention. FIG. 22 shows a T-shape studied by the present inventors. FIG. 23 is a plan view showing a U-groove pattern photomask in which the groove width enlarging effect at the intersection is reduced. FIG. 23 is a cross-sectional view showing an example in which the isolation according to the present invention is applied to a semiconductor integrated circuit device having no shallow groove FIG. 24 is a sectional view showing an example in which the isolation according to the present invention is applied to a semiconductor integrated circuit device using an SOI substrate. FIG. 25 is a semiconductor integrated circuit using an SOI substrate having no shallow groove. FIG. 4 is a longitudinal sectional view showing an example in which the isolation of the present invention is applied to the device. 1 ... silicon single crystal substrate, 2 ... silicon oxide film, 3
... Photoresist film for element region formation, 4... CVD insulating film, 4a... ... Submicron U groove opening, 8 ... Submicron U groove, 10 ... Silicon oxide film, 11 ... Silicon nitride film,
12: CVD oxide film, 20: Submicron U-groove plane pattern.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masataka Miyama 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Seiichiro Higashi 5-2-1, Josuihoncho, Kodaira-shi, Tokyo (72) Inventor Osamu Kasahara 2326 Imai, Ome-shi, Tokyo In-house Device Development Center, Hitachi, Ltd. (72) Inventor Shinichi Suzuki 2326 Imai, Ome-shi, Tokyo Address Device Development Center, Hitachi, Ltd. (56) References JP-A-59-124141 (JP, A) JP-A-64-50540 (JP, A)

Claims (1)

(57) [Claims] A step of forming a first groove in a main surface of the semiconductor substrate so as to surround a region of the main surface of the semiconductor substrate in which an active element is to be formed, and a step of forming a first groove in a bottom surface of the first groove. Forming a second groove narrower than the groove; and depositing an insulator on the main surface of the semiconductor substrate by a CVD method.
Deposited to a thickness approximately the same as the depth of the groove of the first and second grooves.
Forming an insulating film in the groove, and etching back the insulating film until the main surface of the semiconductor substrate is exposed, wherein the second groove is formed to a groove width of 0.5 μm or less, and ,
The surface of the insulating film etched back is substantially flat,
In addition, a method for manufacturing a semiconductor integrated circuit device, wherein a bonding interface between insulating films generated by the CVD method is not exposed on the surface.