WO1999059202A1 - Method of forming a field isolation structure in a semiconductor substrate - Google Patents

Method of forming a field isolation structure in a semiconductor substrate

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Publication number
WO1999059202A1
WO1999059202A1 PCT/US1999/001045 US9901045W WO1999059202A1 WO 1999059202 A1 WO1999059202 A1 WO 1999059202A1 US 9901045 W US9901045 W US 9901045W WO 1999059202 A1 WO1999059202 A1 WO 1999059202A1
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WO
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Patent type
Prior art keywords
layer
oxide
spacers
silicon
dielectric
Prior art date
Application number
PCT/US1999/001045
Other languages
French (fr)
Inventor
Frederick N. Hause
Robert Dawson
Charles May
Original Assignee
Advanced Micro Devices, Inc.
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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

A method of forming a field isolation structure in a semiconductor substrate is disclosed. The method includes providing a first dielectric layer over the substrate, forming an opening in the first dielectric layer, forming spacers in the opening, etching a trench in the substrate using the spacers as an etch mask, growing an oxide layer in the trench such that the oxide layer consumes portions of the substrate directly beneath the spacers, depositing a second dielectric layer over the first dieletric layer and the spacers and into the trench after growing the oxide layer, removing the second dielectric layer over the first dielectric layer and the spacers, and removing the first dielectric layer without removing the spacers. Growing the oxide layer laterally shifts the sidewalls of the trench so that corners of the trench are positioned directly beneath the spacers. Thereafter, as an etch is applied that is highly selective of silicon dioxide during the fabrication of submicron devices in active regions adjacent to the trench, the spacers provide an etch mask that protects the corners, thereby preventing degradation of source/drain regions of the submicron devices.

Description

METHOD OF FORMING A FIELD ISOLATION STRUCTURE IN A SEMICONDUCTOR SUBSTRATE

TECHNICAL FIELD

The present invention relates to integrated circuit manufacturing, and more particularly to field isolation in semiconductor substrates.

BACKGROUND ART

In complex integrated circuits, several hundred thousand or millions of active devices (transistors, capacitors, diodes, resistors, etc.) are fabricated on a single monolithic substrate, and an interconnect structure that includes patterned conductive lines is fabricated for interconnecting the active devices according to a specific circuit function. Typically, the active devices are formed in active regions of the substrate, and the active regions are separated by field regions of the substrate. Insulated-gate field-effect- transistors (IGFETs) are generally self-isolated provided the source and drain are reverse- biased with respect to the substrate. However, field dielectrics are usually formed in the field regions to prevent refractory metal from reacting with the field region, thereby avoiding silicide bridges between active regions. Furthermore, field dielectrics are usually thick enough to prevent overlying conductive lines from forming channels in the field regions, thereby avoiding parasitic devices in the field regions. Field dielectrics are often on the order of 2000 to 5000 angstroms thick.

LOCOS is a well-known technique for providing field dielectrics. LOCOS includes forming a pad oxide over the substrate, forming a nitride layer over the pad oxide, etching the nitride layer over the field regions, and thermally growing the pad oxide over the field regions. LOCOS can be carried out using many different process flows, including semi-recessed or fully-recessed techniques, and poly buffered techniques which use polysilicon between the pad oxide and the silicon nitride to reduce stress induced crystal defects in the substrate during oxidation. However, LOCOS has several drawbacks. For instance, bird' s beak encroachment at the edge of each field region can cause submicron active regions to virtually disappear unless rework is done. Crystal - 2 - defects can occur during oxidation. Oxidation-enhanceddiffusion can cause perpendicular segregation of shallow channel-stop implants such as boron. In addition, Kooi ribbons of silicon nitride can form on the active regions due to the reaction of NH3 (which diffuses through the pad oxide) and the silicon surface. Since Kooi ribbons degrade gate oxide quality, often a sacrificial oxide must be formed and stripped to remove the Kooi ribbons before growing the gate oxide.

Shallow refilled trench structures with depths of less than one micron have been developed as a replacement for LOCOS. For instance, buried-oxide (BOX) isolation technology uses shallow trenches refilled with silicon dioxide deposited by chemical vapor deposition (CVD). In the basic BOX process, a patterned silicon dioxide layer is formed on the substrate, trenches are etched in the substrate using the patterned silicon dioxide layer as an etch mask, another silicon dioxide layer is blanket deposited over the substrate by chemical vapor deposition and fills the trenches, two layers of photoresist are applied with the first being flowed to form a planar top surface, and a reactive ion etch is applied which etches the silicon dioxide and the photoresist at the same rate so that the remaining silicon dioxide remains only in the trenches. The reactive ion etch typically overetchesthe CVD oxide to ensure it is completely removed from the active regions, thereby exposing the sidewalls of the active regions. Advantageously, the basic BOX process eliminates bird' s beak encroachment. However, the basic BOX process has several drawbacks, including void formation if the trenches are narrower than about 2 microns, inversion of the silicon at the sidewalls of the P-type active regions, a non-planar top surface particularly if there is a wide range of sizings and spacings of the active regions, and exposure of the active region sidewalls. Exposure of active region sidewalls adj acent to the gate can lead to parasitic conduction (observable in subthreshold device characteristics) as well as higher electric fields and ensuing hot carrier effects in the gate oxide. Exposure of the active region sidewalls at the edges of the source/drain regions spaced from the gate can lead to increased leakage currents and short circuits between the substrate and silicide contacts.

Modifications to the basic BOX process have been devised to alleviate these problems. For instance, high-temperature CVD oxide that gives conformal coverage - 3 - without void formation has been reported. A shallow-angle implant (7° to the sidewall) of boron has been used to eliminate sidewall inversion of P-type active regions by increasing the threshold voltage of the parasitic N-channel that occurs along the sidewall.

A known modification of the basic BOX process that attempts to avoid exposing the active region sidewalls after the trench is filled includes forming a pad oxide on the substrate, forming a silicon nitride layer on the pad oxide, forming a patterned photoresist layer on the silicon nitride layer, applying an etch using the photoresist layer as an etch mask to remove the exposed portions of the silicon nitride layer and the pad oxide and to form a trench in the substrate, removing the photoresist layer, growing a thermal oxide in the trench, depositing CVD oxide over the structure and into the remaining space in the trench, polishing the CVD oxide so that the CVD oxide and the silicon nitride layer form a planar top surface, and removing the silicon nitride layer. After the silicon nitride layer is removed, it might appear that the CVD oxide assures that the sidewalls are protected from subsequent processing steps. In particular, the CVD oxide may be sufficiently thick that during an anisotropic spacer etch, used to form oxide spacers adj acent to polysilicon gates, a portion of the CVD oxide remains above the substrate although an upper portion of the CVD oxide is removed.

A primary shortcoming of this approach is that the CVD oxide may provide little or no protection for the source/drain sidewalls during the spacer etch due to lateral shifting of the sidewalls as the thermal oxide is grown. Generally speaking, the density reported for thermal oxide is close to that of silicon. These densities, coupled with respective molecular weights of 60 and 28 for oxide and silicon, dictate that for every volume of silicon oxidized, about 2.2 volumes of oxide will be generated. Therefore, silicon is consumed and the top of the oxide rises above the original silicon surface. Oxide growth depends on many factors including oxidation time, oxidizing ambient, ambient pressure and/or temperature, doping in the silicon, stress on the oxide and the silicon, and the area of silicon exposed to the ambient. In the modified BOX process described above, a danger exists that the thermal oxide may laterally shift the sidewalls directly beneath the silicon nitride, such that after the silicon nitride is removed, the CVD oxide is laterally displaced from and fails to protect the sidewalls (or the thermal oxide adjacent to the - 4 - sidewalls) from the spacer etch. As a result, the spacer etch can quickly remove the pad oxide and then remove the thermal oxide adj acent to the source/drain sidewalls, thereby exposing the source/drain sidewalls and causing the problems mentioned above.

Accordingly, a need exists for an improved method of making a field isolation structure for active regions in a substrate that avoids bird' s beak encroachment and other problems associated with LOCOS and that adequately protects the adjacent source/drain sidewalls from exposure during subsequent processing steps.

DISCLOSURE OF INVENTION

An object of the present invention is provide an improved field isolation structure for a semiconductor substrate that addresses the aforementioned need. Generally speaking, the field isolation structure of the present invention addresses this need by forming spacers that define upper corners of the trench as the trench is etched, laterally shifting the corners beneath the spacers during a thermal oxidation step, and using the spacers to protect the laterally shifted corners during subsequent processing steps.

In accordance with one aspect of the invention, a method of forming a field isolation structure includes providing a first dielectric layer over a semiconductor substrate, forming an opening in the first dielectric layer, forming spacers in the opening, etching a trench in the substrate using the spacers as an etch mask, growing an oxide layer in the trench such that the oxide layer consumes portions of the substrate directly beneath the spacers, depositing a second dielectric layer over the first dielectric layer and the spacers and into the trench after growing the oxide layer, removing the second dielectric layer over the first dielectric layer and the spacers, and removing the first dielectric layer without removing the spacers.

Growing the oxide layer laterally shifts the sidewalls of the trench so that upper corners of the trench are positioned directly beneath the spacers. Thereafter, an etch is applied that is highly selective of the thermal oxide during the fabrication of submicron devices in active regions adjacent to the trench, and the spacers provide an etch mask that protects the corners, thereby preventing degradation of source/drain regions of the submicron devices. - 5 -

Preferably, the first dielectric layer is formed on a third dielectric layer which is formed on the substrate, etching the trench includes using both the first dielectric layer and the spacers as an etch mask, growing the oxide layer laterally shifts opposing sidewalls of the trench so that they are disposed directly beneath the spacers, removing the second dielectric layer over the first dielectric layer and the spacers includes polishing the second dielectric layer so that the first dielectric layer, the second dielectric layer and the spacers form a planar top surface, and the spacers are a permanent part of the field isolation structure.

As exemplary materials, the first dielectric layer and the spacers are different nitrogen-bearing materials such as of silicon nitride and silicon oxynitride, and the second and third dielectric layers are silicon dioxide.

Advantageously, the nitrogen-bearing spacers cover the sidewalls of the source/drain regions and the thermal oxide adj acent thereto, and therefore protect these areas from subsequent processing steps such as an anisotropic spacer etch that is highly selective of silicon dioxide and that might otherwise expose the sidewalls of the source/drain regions.

These and other objects, features and advantages of the invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follows.

BRIEF DESCRIPTION OF DRAWINGS

The following detailed description of the preferred embodiments can best be understood when read in conjunction with the following drawings, in which:

Figures 1 A-l J show cross-sectional views of successive process steps for forming a field isolation structure between IGFETs in adjacent active regions of a substrate in accordance with an embodiment of the invention. - 6 -

MODES FOR CARRYING OUT THE INVENTION

In the drawings, depicted elements are not necessarily drawn to scale and like or similar elements may be designated by the same reference numeral throughout the several views.

In Figure 1 A, silicon substrate 102 suitable for integrated circuit manufacture is provided. Substrate 102 includes a P- type epitaxial surface layer with a planar top surface on a P+ base layer (not shown). The epitaxial surface layer has a boron background concentration on the order of 1 x 10 atoms/cm , a <100> orientation and a resistivity of 12 ohm-cm. Pad oxide layer 104, composed of silicon dioxide (SiO2) with a thickness in the range of 100 to 500 angstroms, is grown on substrate 102 using tube growth at a temperature in the range of 700 to 1000°C in an O2 containing ambient. Pad oxide 104 reduces stress related defects in substrate 102. Thereafter, nitride layer 106, composed of silicon nitride (Si3N ) with a thickness in the range of 500 to 2000 angstroms, is deposited on pad oxide 104 by plasma enhanced chemical vapor deposition at a temperature in the range of200 to 400°C.

In Figure IB, photoresist layer 108 is deposited on nitride layer 106. A photolithographic system, such as a step and repeat optical projection system which generates deep ultraviolet light from a mercury-vapor lamp, irradiates photoresist layer 108 with an image pattern. Thereafter, the irradiated portions of photoresist layer 108 are removed, and photoresist layer 108 includes an opening above a field region of substrate 102. For illustration purposes, the length of the opening in photoresist layer 108, is about 3500 angstroms (0.35 microns).

In Figure 1C, an anisotropic dry etch is applied using photoresist layer 108 as an etch mask. Photoresist layer 108 protects the underlying regions of nitride layer 106, and the etch removes the region of nitride layer 106 beneath the opening in photoresist layer 108. The etch is highly selective of silicon nitride with respect to silicon dioxide, so only a negligible amount of pad oxide layer 104 is removed and substrate 102 is unaffected.

In Figure ID, photoresist layer 108 is stripped, and then an oxynitride layer, composed of silicon oxynitride (SL yN^ with a thickness of 1500 angstroms, is - 7 - conformally deposited over the exposed surfaces by plasma enhanced chemical vapor deposition at a temperature in the range of 200 to 400°C . Thereafter, the entire oxynitride layer is subjected to an anisotropic reactive ion etch that is highly selective of silicon oxynitride with respect to silicon nitride and silicon dioxide, and the unetched portions of the oxynitride layer form spacers 110 and 112 adj acent to and between the opposing sidewalls of nitride layer 106. Spacers 110 and 112 are disposed on pad oxide 104 and each have a length (laterally extending from nitride layer 106) in the range of 200 to 400 angstroms. Thus, spacers 110 and 112 are separated from one another by about 2700 (3500 - 800) to 3100 (3500 - 400) angstroms, and the portion of pad oxide 104 between spacers 110 and 112 is exposed.

The dimensions of spacers 110 and 112 depend on several variables, including the thickness of nitride layer 106, the thickness of the oxynitride layer, and the duration of the spacer etch. In the present embodiment, the lengths of spacers 110 and 112 are selected to exceed the lateral shifting of subsequently formed trench sidewalls during a thermal oxidation step, as described below.

In Figure IE, an anisotropic dry etch is applied using nitride layer 106 and spacers 110 and 112 as an etch mask. Initially, the etch is highly selective of silicon dioxide with respect to silicon nitride and silicon oxynitride so that pad oxide 104 between spacers 110 and 112 is removed and only a negligible amount of substrate 102, nitride layer 106 and spacers 110 and 112 is removed. Thereafter, the etch becomes highly selective of silicon with respect to silicon nitride and silicon oxynitride so that trench 114 is formed in substrate 102 and only a negligible amount of nitride layer 106 and spacers 110 and 112 is removed. The etch is carefully timed so that trench 114 has a depth in the range of 2000 to 5000 angstroms relative to the top surface of substrate 102. Trench 114 includes opposing sidewalls 116 and 118 that are aligned with the outer edges of spacers 110 and 112, respectively. Thus, sidewalls 116 and 118 form upper corners adj acent to the top surface of substrate 102 and lower corners adj acent to the bottom surface of trench 114. Sidewalls 116 and 118 are essentially vertical although they may taper slightly as a function of the etch and the lattice orientation of substrate 102. Advantageously, the - 8 - length between sidewalls 116 and 118 is about 2700 to 3100 angstroms, which is smaller than the length of the opening in photoresist layer 108.

In Figure IF, thermal oxide 120, composed of silicon dioxide with a thickness in the range of 300 to 500 angstroms, is grown on the exposed surfaces of trench 114 using tube growth at a temperature in the range of 700 to 1000°C in an O2 containing ambient. In addition, a negligible amount (30 to 50 angstroms) of oxidation forms on the exposed surfaces of nitride layer 106, which is not shown for convenience of illustration. Thermal oxide 120 provides a dense, high quality liner oxide that reduces etch damage to substrate 102 by reducing dangling silicon atoms (that cause leakage paths) and surface adsorbed etch gases (that cause contamination) . Thermal oxide 120 occupies a minor portion of the space in trench 114 leaving most of the space in trench 114 unfilled. Moreover, thermal oxide 120 consumes about 135 to 230 angstroms of the adjacent surfaces of substrate 102 since about 2.2 volumes of oxide are generated for every volume of silicon consumed during thermal oxidation. As a result, sidewalls 116 and 118 each laterally shift about 135 to 230 angstroms away from each other to positions directly beneath spacers 110 and 112, respectively. Accordingly, the upper corners between sidewalls 116 and 118 and the top surface of substrate 102 are positioned directly beneath spacers 110 and 112, respectively, and are no longer aligned with spacers 110 and 112, respectively. In addition, portions of thermal oxide 120 adjacent to sidewalls 116 and 118 are also positioned directly beneath spacers 110 and 112. Thus, the thickness of thermal oxide 120 is selected to be less than the lengths of spacers 110 and 112 to prevent sidewalls 116 and 118 from laterally shifting directly beneath nitride layer 106 outside spacers 110 and 112, respectively. After thermal oxide 120 is grown, a channel-stop implant is performed as is conventional.

In Figure 1 G, oxide layer 122, composed of silicon dioxide with a thickness of in the range of 5000 to 14,000 angstroms, is conformally deposited over the exposed surfaces by plasma enhanced chemical vapor deposition at a temperature in the range of 300 to 450°C. Oxide layer 122 has a thickness that is about twice the distance between the top surface of nitride layer 106 and the bottom surface of trench 114 to assure that it completely fills the remaining space in trench 114 and in the opening in nitride layer 106. - 9 -

In Figure 1H, the structure is planarizedby applying chemical-mechanical polishing in the presence of an abrasive slurry that is highly selective of silicon dioxide with respect to silicon nitride and silicon oxynitride. The polishing grinds oxide layer 122 then is discontinued using nitride layer 106 and spacers 110 and 112 as a stop-layer. The polishing also removes about one-third of nitride layer 106 and spacers 110 and 112 to ensure that oxide layer 122 is completely removed above nitride layer 106. After polishing occurs, the top surfaces of nitride layer 106, spacers 110 and 112 and oxide layer 122 are aligned with one another and form a planar surface.

In Figure II, an etch such as hot phosphoric acid is applied that is highly selective of silicon nitride with respect to silicon dioxide and silicon oxynitride, thereby removing nitride layer 106 without removing pad oxide 104, spacers 110 and 112, or oxide layer 122.

At this stage, the field isolation structure is complete. As is seen, spacers 110 and 112 are positioned directly above sidewalls 116 and 118, respectively, and therefore protect sidewalls 116 and 118 from subsequent processing steps.

The description that follows illustrates a conventional method of forming insulated-gate field-effect transistors (IGFETs) in active regions of substrate 102 adj acent to the field isolation structure whereby spacers 110 and 112 protect sidewalls 116 and 118, respectively, from etch steps that might otherwise expose them. It is understood that the field isolation structure of the present invention can be used with a wide variety of IGFET manufacturing techniques.

In Figure 1J, active regions 124 and 126 in substrate 102 are adj acent to sidewalls 116 and 118, respectively, and are separated from one another by the field isolation structure . Active regions 124 and 126 are subj ected to a well implant of arsenic to provide them with a background doping concentration on the order of 1 x 10 atoms/cm . If desired, suitable threshold-adjust and punchthrough implants can also be applied. Thereafter, pad oxide 104 outside spacers 110 and 112 is etched and removed. The pad oxide etch is highly selective of silicon dioxide with respect to silicon and silicon oxynitride and removes a significant portion of oxide layer 122 but only a negligible - 10 - amount of substrate 102 and spacers 110 and 112. The top surface of oxide layer 122 after the pad oxide etch is illustrated by broken lines 128. Since, however, spacers 110 and 112 are resistant to the pad oxide etch, spacers 110 and 112 protect sidewalls 116 and 118, respectively, and the underlying portions of thermal oxide 120 from the pad oxide etch. Thereafter, gate oxides 130 and 132 composed of silicon dioxide with a thickness of 50 angstroms are thermally grown on active regions 124 and 126. A blanket layer of polysilicon with a thickness of about 2000 angstroms is then deposited over the structure by chemical vapor deposition, and gates 134 and 136 are formed from unetched portions of the polysilicon layer over active regions 124 and 126, respectively, using photolithography and an etch step. Thereafter, lightly doped source/drain regions 140 and 142 are implanted into active regions 124 and 126, respectively, using gates 134 and 136 as an implant mask for active regions 124 and 126, respectively. Lightly doped

17 source/drain regions 140 and 142 have a phosphorus concentration on the order of 1 x 10 to 1x10 atoms/cm .

Thereafter, a blanket layer of silicon dioxide is deposited over the structure by chemical vapor deposition and an anisotropic reactive ion etch is applied to form spacers 144 and 146 from unetched portions of the oxide layer adj acent to the sidewalls of gates 134 and 136, respectively. The spacer etch is highly selective of silicon dioxide with respect to silicon, polysilicon and silicon oxynitride, and removes significant portions of thermal oxide 120 and oxide layer 122 but only a negligible amount of substrate 102, spacers 110 and 112 and gates 134 and 136. The recessed upper portions of thermal oxide 120 and the top surface of oxide layer 122 after the spacer etch are illustrated by broken lines 148. As is seen, broken lines 148 extend below the top surface of substrate 102 into the trench. Since, however, spacers 110 and 112 are resistant to the spacer etch, and the spacer etch is anisotropic, spacers 110 and 112 protect sidewalls 116 and 118, respectively, and the underlying portions of thermal oxide 120 from the spacer etch. Thus, the recessed upper portions of thermal oxide 120 are aligned with spacers 110 and 112, and sidewalls 116 and 118 remain unexposed. In the absence of spacers 110 and 112, portions of thermal oxide 120 adjacent to the top surface of substrate 102 would be completely removed, and portions of sidewalls 116 and 118 adj acent to the top surface of substrate 102 would be exposed. - 11 -

Thereafter, heavily doped source/drain regions 150 and 152 are implanted into active regions 124 and 126, respectively, using gate 134 and spacers 144 as an implant mask for active region 124 and using gate 136 and spacers 146 as an implant mask for active region 126. Heavily doped source/drain regions 150 and 152 have an arsenic concentration on the order of 1x10 to 1x10 atoms/cm . The device is then subj ected to a rapid thermal anneal on the order of 950 to 1050°C for 10 to 30 seconds to drive-in and activate the implanted dopants. The anneal diffuses lightly doped source/drain regions 140 and 142 beneath gates 134 and 136, respectively, heavily doped source/drain regions 150 and 152 beneath spacers 144 and 146, respectively, one of heavily doped source/drain regions 150 beneath spacer 110, and one of heavily doped source/drain regions 152 beneath spacer 112. In this manner, an N-channel enhancement-modelGFET is formed in active region 124 with a source and drain (consisting of lightly and heavily doped source/drain regions 140 and 150) controlled by gate 134, and an N-channel enhancement-modelGFET is formed in active region 126 with a source and drain (consisting of lightly and heavily doped source/drain regions 142 and 152) controlled by gate 136.

Providing low resistance contacts for the gates, sources and drains can be accomplished using a refractory metal silicide. In one approach, a thin layer of refractory metal is deposited over the structure, and heat is applied to form silicide contacts wherever the refractory metal is adjacent to silicon (including single crystal silicon and polysilicon). This forms silicide contacts 154 for the gate, source and drain at active region 124 and silicide contacts 156 for the gate, source and drain at active region 126. Thereafter, an etch is applied that removes unreacted refractory metal over the spacers to prevent bridging the silicide contacts. Various suicides such as titanium silicide (TiSi2), tungsten silicide (WSi2), molybdenum silicide (MoSi2), cobalt silicide (CoSi2) and tantalum silicide (TaSi2) have been used for this purpose. For instance, the sheet resistance of titanium silicide is as low as 3 to 6 Ω/sq, whereas heavily doped polysilicon exhibits a sheet resistance on the order of 15 to 30 Ω/sq. Another advantage to this approach is that the silicide contacts are formed simultaneously and are self-aligned by spacers 144 and 146. This self-aligned silicide is often referred to as salicide. - 12 -

Of importance, broken lines 148 extend below heavily doped source/drain regions 150 and 152. In the absence of spacers 110 and 112, the silicide contacts on heavily doped source/drain regions 150 and 152 would contact substrate 102 below heavily doped source/drain regions 150 and 152, thereby rendering the IGFETs unsatisfactory or inoperable. Advantageously, spacers 110 and 112 prevent this from happening.

Further processing steps in the fabrication of IGFETs typically include forming a thick dielectric layer over the structure (thereby filling any space in trench 114), planarizing the thick dielectric layer, forming contact windows in the thick dielectric layer to expose the silicide contacts, forming conductive plugs in the contact windows, and forming additional layers of interconnect metallization (such as metal- 1 through metal-5), conductive plugs, and interlayer dielectrics above the structure. In addition, earlier or subsequent high-temperature process steps can be used to supplement or replace the anneal step to provide the desired anneal, activation, and drive-in functions. These further processing steps are conventional. Likewise the principal processing steps disclosed herein may be combined with other steps apparent to those skilled in the art.

The present invention includes numerous variations to the embodiment described above. For instance, the portion of pad oxide 104 in the opening in nitride layer 106 can be removed before forming spacers 110 and 112. In this case, spacers 110 and 112 are formed directly on substrate 102, and photoresist layer 108 can be removed either before or after removing pad oxide 104. Alternatively, pad oxide 104 can be omitted, in which case nitride layer 106 and spacers 110 and 112 are formed directly on substrate 102.

Furthermore, the first dielectric layer (e.g., nitride layer 106), the second dielectric layer (e.g., oxide layer 122) and the spacers (e.g., spacers 110 and 112) can be various materials such as silicon dioxide, silicon nitride, silicon oxynitride, and other materials. Preferably, the first dielectric layer and the spacers are nitrogen-bearing materials, and the second dielectric layer is essentially devoid of nitrogen. It is also preferred that the first dielectric layer and the spacers are different materials so that the first dielectric layer can be selectively etched with respect to the spacers, and the second dielectric layer and the spacers are different materials so that the spacers are resistant to a subsequent etch that attacks the second dielectric layer. The etch mask (e.g., photoresist layer 108) for the first - 13 - dielectric layer can be a hard mask patterned by photoresist. The thermal oxide can be grown either before or after the channel-stop implant. Likewise, the field isolation structure can be formed either before or after the well, punchthrough and/or threshold- adjust implants. The field isolation structure can be located between active devices such as symmetrical or asymmetrical N-channel or P-channel transistors either with or without lightly doped drains. Suitable N-type dopants include arsenic and phosphorus; suitable P- type dopants include boron B 10, boron n, and BFX species such as BF .

If desired, the planarity of the second dielectric layer can be improved by forming a reverse mask (with a pattern opposite to photoresist layer 108) over the second dielectric layer, partially etching the second dielectric layer outside the field isolation structure using the reverse mask as an etch mask, and removing the reverse mask. This reduces dishing of the second dielectric layer over the trench during the polishing step. Furthermore, in the event dishing removes an upper portion of the second dielectric layer in the trench without removing a lower portion of the second dielectric layer in the trench, it is understood that that second dielectric layer has not been removed from the trench.

The invention is particularly well-suited for fabricating field isolation structures in high-performance microprocessors where high circuit density is essential. Although a single field isolation structure has been shown for purposes of illustration, it is understood that in actual practice, many field isolation structures are fabricated on a single semiconductor wafer as widely practiced in the art. Accordingly, the invention is well- suited for use in an integrated circuit chip, as well as an electronic system including a microprocessor, a memory and a system bus.

Those skilled in the art will readily implement the steps necessary to provide the structures and methods disclosed herein, and will understand that the process parameters, materials, and dimensions are given by way of example only and can be varied to achieve the desired structure as well as modifications which are within the scope of the invention. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims.

Claims

- 14 -WE CLAIM:
1. A method of forming a field isolation structure in a semiconductor substrate, comprising the steps of: providing a semiconductor substrate; providing a first dielectric layer over the semiconductor substrate; forming an opening in the first dielectric layer; forming spacers in the opening ; etching a trench in the substrate using the spacers as an etch mask; growing an oxide layer in the trench such that the oxide layer consumes portions of the substrate directly beneath the spacers ; depositing a second dielectric layer over the first dielectric layer and the spacers and into the trench after growing the oxide layer; removing the second dielectric layer over the first dielectric layer and the spacers; and removing the first dielectric layer without removing the spacers.
2. The method of claim 1 , wherein the first dielectric layer is formed on a third dielectric layer, and the third dielectric layer is formed on the substrate.
3. The method of claim 1 , wherein forming the opening in the first dielectric layer includes forming an etch mask over the first dielectric layer and applying an anisotropic etch through an opening in the etch mask.
4. The method of claim 1 , wherein the spacers are formed adj acent to opposing sidewalls of the first dielectric layer in the opening.
5. The method of claim 1 , wherein etching the trench includes using the first dielectric layer as an etch mask. - 15 -
6. The method of claim 1 , wherein etching the trench provides sidewalls for the trench that are substantially aligned with the spacers, and growing the oxide layer laterally shifts the sidewalls directly beneath the spacers.
7. The method of claim 1 , wherein removing the second dielectric layer includes polishing the second dielectric layer.
8. The method of claim 1 , including applying an etch that is highly selective of the oxide using the spacers as an etch mask for the comers after removing the first dielectric layer.
9. The method of claim 8, wherein the etch that is highly selective of the thermal oxide removes a substantial portion of the second dielectric layer in the trench without exposing the comers.
10. A field isolation structure in a semiconductor substrate, comprising: a thermal oxide liner contacting a bottom surface and opposing sidewalls of a trench in a semiconductor substrate, wherein the trench includes comers between the sidewalls and a top surface of the substrate; a dielectric material on the thermal oxide liner and disposed in the trench; and spacers directly above the comers .
PCT/US1999/001045 1998-05-08 1999-01-18 Method of forming a field isolation structure in a semiconductor substrate WO1999059202A1 (en)

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