JPH0665221B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which characteristics such as prevention of a parasitic channel are improved while achieving high integration.

[Background technology]

With the recent increase in the degree of integration of semiconductor devices, especially semiconductor integrated circuits, a groove isolation structure has been adopted instead of the element isolation technique by the selective oxidation method using a silicon nitride film as a mask. In this groove type isolation structure, a deep groove 52 having a narrow width is formed on the surface of a semiconductor substrate 51 as shown in FIG. 4, an insulating film 53 is formed on the inner surface of the groove 52, and a polysilicon 54 or the like is buried inside. With the above structure, the MIS transistor 55 formed in the active region is isolated. In this example, a P-type well 56 is formed in the N-type semiconductor substrate 51, source / drain regions 57 and 58 are formed of N-type impurity layers in the well 56, and a gate insulating film 59 is formed.
An N-type MOS transistor 55 is formed by forming a gate electrode 60 on it. According to such a groove type isolation structure, so-called bird's beaks are not generated, element miniaturization and high integration can be realized, and the isolation region exists up to a deep position of the substrate. Therefore, the complementary MISFET (C- It is effective in preventing the latch-up phenomenon in MIS).

However, in this groove type isolation structure, as shown in the equivalent circuit of FIG.
There is a possibility that 1, Tr2, Tr3 may be formed, and a problem that a leak current flows and the device characteristics deteriorate is likely to occur. That is, the transistor Tr1 has a source 57 as a source, a well 56 as a channel, a substrate 51 as a drain and gate, and a vertical parasitic transistor on the source side, a transistor Tr2 a drain 58 as a source, a well 56 as a channel, a substrate 51 as a drain and a gate. And a vertical parasitic transistor on the drain side,
The transistor Tr3 is a parasitic transistor in the channel direction along the side surface of the groove 52. Further, in some cases, as a result of being formed in the substrate 51 due to the stress at the time of forming the groove or filling the groove, a leak current or the like due to a defect is generated.

The cause of the leak current due to such a parasitic transistor and crystal defects is that effective parasitic channel prevention is not performed. That is, in the above-mentioned groove type isolation, the impurity layer (P-type layer) 61 for preventing the parasitic channel is formed only on the bottom of the groove 52 by performing ion implantation on the bottom of the groove 52 after forming the groove 52, or on the substrate. Whether or not the impurity layer (P-type layer) 62 is formed only on the surface of the groove 51
This is because the impurity layer that covers the entire side surface of 52 cannot be formed. Furthermore, when separating the NMIS portion and the PMIS portion of the complementary MISFET, it is impossible to individually form an impurity layer of a conductive type effective for each MIS portion.

Regarding this parasitic transistor, for example, R, D, Rung
et al, IEDM IEEE 1982, p237-240.

[Object of the Invention]

It is an object of the present invention to prevent the occurrence of a parasitic channel in a groove type isolation structure, and at the same time, to improve the characteristics by preventing a leak current, and, on the other hand, to form the groove by a self-alignment method. It is an object of the present invention to provide a method of manufacturing a semiconductor device, which can achieve high integration by miniaturizing an element isolation region.

The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of the present specification and the accompanying drawings.

[Outline of Invention]

The following is a brief description of the outline of the typical invention disclosed in the present application.

According to a method of manufacturing a semiconductor device of the present invention, a deep groove formed in a semiconductor substrate is subjected to an insulation treatment to form a groove type isolation for element isolation, and semiconductor elements of different conductivity types are provided on both sides of the groove so as to sandwich the groove. When forming, the following (A) ~
Each step (I) is provided.

(A) SiO ₂ film, Si on the entire surface of the first conductivity type semiconductor substrate
After sequentially forming the ₃ N ₄ film, the CVDSiO ₂ film and the first Al film, the 1Al film, the CVDSiO ₂ film and the Si ₃ N ₄ film are formed by isotropic etching using the resist formed on the first Al film as a mask. Etching them so that their width is smaller than the width of the resist.

(B) After forming a second Al film on the entire surface of the semiconductor substrate and removing the resist together with the second Al film thereon,
Using the second Al film remaining on the semiconductor substrate and the first Al film under the resist as a mask, the SiO ₂ film and the semiconductor substrate in a portion corresponding to the eaves of the resist are anisotropically etched to form a first groove. Forming step.

(C) After removing the first and second Al films and diffusing a first conductivity type impurity in the first groove to form a first conductivity type impurity layer as a channel stopper layer, Oxidizing the inside of the groove to form a Si ₂ film on the surface of the first conductivity type impurity layer.

(D) Using the CVDiO ₂ film as a mask for ion implantation, diffusing a second conductivity type impurity into the semiconductor substrate,
Forming a well of the second conductivity type in a region shallower than the trench.

(E) Polysilicon is formed on the entire surface of the semiconductor substrate to fill the first trench, and then the polysilicon is anisotropically etched to form the CVDSiO ₂ film.
Forming polysilicon sidewalls that are located slightly inside both sides of the first trench in which both sidewalls of the film are filled with polysilicon.

(F) a SiO ₂ film according 3Al film and ECR plasma method are sequentially formed on the entire surface of the semiconductor substrate, by wet-etching the SiO ₂ film by the ECR plasma method,
After opening windows on both sides of the sidewall, the ECR
A step of etching the third Al film in the window using the SiO ₂ film formed by the plasma method as a mask, and then removing the SiO ₂ film formed by the ECR plasma method.

(G) A second groove is formed in a region partially overlapping with the first groove by anisotropically etching the semiconductor substrate using the third Al film remaining on the semiconductor substrate as a mask. Process.

(H) Impurity of the second conductivity type is diffused in the second groove to form a second conductivity type impurity layer as a channel stopper layer, and the second groove is oxidized to form the second conductivity type. A step of forming a SiO ₂ film on the surface of the type impurity layer.

(I) The third Al film, the sidewall, the CVDSiO
After removing the _second film and the Si ₃ N ₄ film, the polysilicon is etched back to fill the second groove, and then a SiO ₂ film is formed on the surface of the polysilicon to form the groove-shaped isolator. Process to complete the ration.

[Embodiment 1] FIG. 1 is a schematic perspective view of an embodiment in which the present invention is applied to a semiconductor device of a complementary MISFET. Groove type isolation 2 is formed on N type silicon substrate 1 to form NMIS transistor 3
And the PMIS transistor 4 are formed separately. The NMIS transistor 3 has a P-type well 5 formed on the silicon substrate 1,
Source / drain regions 6, 6 made of N-type impurity layers are formed in the P-type well 5, and a gate electrode 8 made of polysilicon is formed on the gate insulating film (SiO ₂ 7).
Further, in the PMIS transistor 4, source / drain regions 9, 9 made of P-type impurity layers are formed on the silicon substrate 1, and a gate electrode 11 is formed on the gate insulation 10.

The groove type isolation 2 is formed in a deep groove, and an insulating film 12 of SiO ₂ is formed on the surface and the center of the deep groove, and polysilicon (or SiO ₂ ) 13 is embedded and buried in the remaining portion. .
Further, an insulating film 14 continuous with the gate insulating films 7 and 10 is formed on the surface to prevent the exposure of the polysilicon 13. The same conductivity type (P) as that of the well 5 is provided over the entire side surface or bottom surface of the trench isolation 2 on the NMIS transistor 3 side.
(Type) impurity layer 15 is formed, and on the other hand, the same conductivity type (N-type) impurity layer 16 as the substrate 1 is formed over the entire side surface or bottom surface on the PMIS transistor 4 side.
It is configured as a channel stopper for 3 and 4.

Therefore, according to this configuration, in the NMIS transistor 3 in which the parasitic channel is a problem, the P-type well 5
Since the P-type impurity layer 15 is formed on the side surface of the groove type isolation 2 over the entire depth of, the generation of the above-mentioned parasitic transistors Tr1, Tr2, Tr3, that is, the generation of the parasitic channel can be prevented. Similarly, also in the PMIS transistor 4, the N-type impurity layer 16 on the side surface of the trench isolation 2 is formed.
This can prevent the occurrence of parasitic channels. Further, in the groove type isolation 2, the impurity layers 15 and 16 on the NMIS transistor 3 side and the PMIS transistor 4 side have different conductivity types, so that a leak current through these impurity layers 15 and 16 can be prevented. In particular, crystal defects due to stress or the like are likely to occur in the vicinity of the groove isolation 2, but the leak current can be effectively suppressed by the crystal defects. Of course, it is needless to say that the circuit element can be miniaturized due to the groove type isolation structure.

2A to 2H are views showing a method of manufacturing the semiconductor device of FIG.

First, as shown in FIG. 1A, a silicon oxide (SiO ₂ ) film 20 and a silicon nitride (Si ₃ N ₄ ) film 2 are formed on the surface of the N-type silicon substrate 1.
1 and the SVDSiO ₂ film 22 are sequentially stacked, and the CVPSiO ₂ film 22 is patterned by a lithography technique using a resist (not shown). Then, using this as a mask, a highly anisotropic dry etching such as RIE is performed to form a deep first groove 23 in the surface of the silicon substrate 1. The CVDSiO ₂ 22 is then removed by etching.

Next, the silicon substrate 1 is heat-treated in an N-type impurity atmosphere such as P (phosphorus) to diffuse impurities from the inner surface of the first groove 23 to the substrate 1 along the periphery (side surface, bottom surface) of the groove 23. The N-type impurity layer 16 is formed as shown in FIG. At this time,
Impurities are not diffused on the surface of the substrate 1 by the SiO ₂ film 20 and Si ₃ N ₄ 21.

Next, the exposed inner surface of the first groove 23 is oxidized to form SiO ₂
A film 12a is formed as shown in FIG. 3C, and the first groove 23 is filled with polysilicon 13. Instead of polysilicon 13
CVDSiO ₂ may be used, and as a filling method, a method of leaving polysilicon or CVDSiO ₂ only in the groove 23 by depositing polysilicon or CVDSiO _{2 on} the surface of the substrate 1 and etching back the same is used. Thereafter the Si ₃ N ₄ film 21 as shown in FIG. (D)
Is removed, and a Si ₃ N ₄ film 24 is newly formed on the entire surface.

Next, as shown in FIG. 7E, a CVD SiO ₂ film 25 is formed, and this is patterned to form a window 25a at a position slightly overlapping the first groove 23. Then, anisotropic etching is performed using the CVD SiO ₂ film 25 as a mask to form a second deep groove 26 as shown in FIG. After removing the CVDSiO ₂ film 25, heat treatment is performed in a P-type impurity atmosphere such as B (boron) to diffuse the P-type impurity from the inner surface of the second groove 26 to the substrate 1 as shown in FIG. Then, P on the side surface and the bottom surface of the second groove 26.
The type impurity layer 15 is formed. At this time, the diffusion is not carried out on the surface of the substrate 1 as in the case described above.
It is not directly related to the substrate 1 even if it is diffused into the polysilicon 13 in 23.

Then, as shown in FIG. 6H, the inner surface of the second groove 26 is oxidized to form the SiO ₂ film 12b, and the polysilicon 13 is filled in the second groove 26 as described above. After removing the Si ₃ N ₄ film 24, the surface of the first and second grooves 23, 26 is oxidized to form the SiO ₂ film 14, thereby completing the groove type isolation 2.

Thereafter, as shown in FIG. 6H, selective ion implantation and diffusion are performed to form a P-type well 5, and gate insulating films 7 and 10, gate electrodes 8 and 11 N-type source / drain regions 6 and 6 are formed by a conventional method. The first semiconductor device can be completed by forming 6 and P-type source / drain regions 9, 9.

[Embodiment 2] FIGS. 3 (A) to 3 (L) are views showing another manufacturing method of the present invention, particularly an example of forming a groove by a self-alignment method.

First, a SiO ₂ film 32 and a Si ₃ N ₄ film 33 are formed on the surface of a silicon substrate 31 by oxidation and nitridation as shown in FIG. 3A, and a low pressure CVD SiO ₂ film 34 and a first Al film 35 are formed on the SiO ₂ film 32 and the Si ₃ N ₄ film 33. Form. Then, after patterning a resist film 36 thereon, the first Al film 35, the low-pressure CVD SiO ₂ film 34, and the Si ₃ N ₄ film are used as a mask.
33 is etched, and is slightly side-etched so as to be smaller than the width of the resist 36 as shown in FIG.

Next, as shown in FIG. 6C, a second Al film 37 is deposited on the entire surface to form a second Al film 37 on the SiO ₂ film 32 and the resist 36. At this time, the second Al film 37 corresponds to the eaves of the resist 36. Of the part
The SiO ₂ film 32 is shaded and the second Al film 37 is not formed. Therefore, the resist 36 is applied to the second Al film 3 on the resist 36.
7 and the first Al film 35 and the SiO ₂ film 32
By anisotropically etching the SiO ₂ film 32 and the substrate 31 using the 2Al film 37 as a mask, deep first grooves 38, 38 as shown in FIG. 9D can be formed.

Then, after removing the first and second Al films 35 and 37, as shown in FIG. 7E, N-type impurities are diffused to form N-type impurity layers 39 and 39 and the inner surface is oxidized as in the previous example. Then, the SiO ₂ films 40, 40 are formed. Further, P-type impurities are ion-implanted into the substrate 31 and diffused using the remaining low-pressure CVD SiO ₂ film 34 as a mask to form P-type wells 41, 41. Then, the same figure (F)
As shown by the chain line, the polysilicon 42 is deposited sufficiently thick to fill the first groove 38, and then anisotropically etched (packed) by the RIE method or the like.
On both sides of the low-voltage SiO ₂ film 34, a part of the sidewalls 43, 43 is formed.
Left as. Both sides of the sidewalls 43, 43 are preferably located slightly inside the both sides of the first groove 38, 38.

Next, as shown in FIG. 3G, a third Al 44 is formed on the entire surface and a SiO ₂ film 45 is formed thereon by the ECR plasma method. If this SiO ₂ film 45 is wet-etched, the corners of the SiO ₂ film 45 of the ECR plasma method will be etched more than others, so that the windows 45a and 45a are opened at the corners as shown in FIG. To be done. Therefore, using this SiO ₂ film 45 as a mask,
When the l film 44 is etched, the third Al film 44 is etched only on both sides of the sidewalls 43, 43 as shown in FIG. The ECR plasma method SiO ₂ film 45 is removed.

Next, by anisotropically etching the substrate 31 using the third Al film 44 as a mask, the first grooves 38, 38 are partially overlapped with each other (at positions on both sides of the first groove). Figure (J)
The second grooves 46, 46 are thus formed. Thereafter, diffusion of P-type impurities is performed as shown in FIG.
P-type impurity layers 47, 47 are formed on the side surfaces and bottom surfaces of 6, 46, and the inner surfaces are oxidized to form a SiO ₂ film 48. The third Al film 44, the sidewalls 43, 43, the low pressure CVD SiO ₂ film 34, and the Si ₃ N ₄ film 33 are removed.

Thereafter, similarly to the above, by filling the second trenches 46, 46 with polysilicon 49, 49 and forming the SiO ₂ films 50, 50 on the surface, the trench type isolator as shown in FIG. Can complete the ration. If the NMIS transistor (3) and the PMIS transistor (4) are formed in this by a conventional method, the semiconductor device of FIG. 1 can be completed.

According to this example, since the second grooves 46, 46 are formed by self-alignment, mask alignment with the first grooves 38, 38 is not necessary, and highly precise and fine groove type isolation can be formed. .

[Effect]

(1) Since the impurity layer as the channel stopper is formed over the entire side surface of the groove type isolation, the parasitic channel can be effectively prevented, the leakage current can be prevented, and the characteristics of the circuit element can be improved.

(2) Since the impurity layers of different conductivity types are formed on both sides of the trench isolation, each MISF of the complementary MISFET is formed.
It can effectively prevent parasitic channels in ET.

(3) Since the impurity layers on both sides of the groove type isolation have different conductivity types, a leak current through the impurity layer can be surely prevented, which is also effective for crystal defects.

(4) Since the groove is formed deep and the above-mentioned parasitic channel preventing effect is obtained, it is effective in preventing latch-up in the complementary MISFET.

(5) Since the first groove is formed and the impurity layer on the side surface thereof is formed, and then the second groove is formed and the impurity layer on the side surface thereof is formed, each impurity layer is formed independently. In particular, it can be easily formed even when the conductivity types of both impurity layers are different.

(6) Since the first and second grooves are formed so as to partially overlap with each other, the width of the groove type isolation can be properly adjusted by controlling the overlapping size.

(7) Since the second groove is formed by the self-aligning method using the mask in which the first groove is formed, the mask alignment of the first and second grooves is unnecessary, and it is highly accurate and fine. A groove type isolation can be formed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. Nor. For example, the first groove and the second groove do not have to have the same depth, and may be formed at least deeper than the well and the impurity layer may be formed over the entire depth of the well. Moreover, since it is difficult to generate a parasitic channel in the PMISFET, the impurity layer on the PMISFET side may be omitted.

[Field of application]

In the above description, the invention mainly made by the present inventor has been described in the case of being applied to the complementary MISFET which is the field of application which is the background of the invention. It can be applied to semiconductor devices such as semiconductor devices in general, and various applications such as combination with an epitaxial substrate can be expected.

[Brief description of drawings]

FIG. 1 is a cutaway perspective view of an apparatus according to an embodiment of the present invention, FIGS. 2A to 2H are process cross-sectional views of an embodiment of a manufacturing method according to the present invention, and FIGS. ) Is a process sectional view of another embodiment of the manufacturing method, FIG. 4 is a cutaway perspective view for explaining a conventional defect, and FIG. 5 is an equivalent circuit diagram showing a parasitic channel in FIG. 1 ... Silicon substrate, 2 ... Groove type isolation, 3
…… NMISFET, 4 …… PMISFET, 5 …… P-type well, 12,1
2a, 12b …… SiO ₂ film, 13 …… Polysilicon, 14 …… SiO
₂ film, 15 …… P-type impurity layer, 20 …… SiO ₂ film, 21 …… Si ₃ N ₄
Film, 22 …… CVD SiO ₂ film, 23 …… First groove, 24 …… Si ₃ N
₄ film, 25 …… CVD SiO ₂ film, 26 …… second groove, 31 …… silicon substrate, 32 …… SiO ₂ film, 33 …… Si ₃ N ₄ film, 34 …… low pressure CVD
SiO ₂ film, 35 …… First Al film, 36 …… Resist, 37 …… Second Al film
Membrane, 38 ... First groove, 39 ... N-type impurity layer, 41 ... P-type well, 43 ... Sidewall, 44 ... Third Al layer, 45 ...
… ECR plasma SiO ₂ film, 46 …… second groove, 47 …… P-type impurity layer.

Claims (1)

[Claims] 1. A deep groove formed in a semiconductor substrate is subjected to an insulation treatment to form groove isolation for element isolation, and when a semiconductor element of different conductivity type is formed on both sides of the groove, the following steps are performed. A method for manufacturing a semiconductor device, comprising the steps (A) to (I). (A) SiO ₂ film, Si on the entire surface of the first conductivity type semiconductor substrate
After sequentially forming the ₃ N ₄ film, the CVDSiO ₂ film and the first Al film, the 1Al film, the CVDSiO ₂ film and the Si ₃ N ₄ film are formed by isotropic etching using the resist formed on the first Al film as a mask. Etching them so that their width is smaller than the width of the resist. (B) After forming a second Al film on the entire surface of the semiconductor substrate and removing the resist together with the second Al film thereon,
Using the second Al film remaining on the semiconductor substrate and the first Al film under the resist as a mask, the SiO ₂ film and the semiconductor substrate in a portion corresponding to the eaves of the resist are anisotropically etched to form a first groove. Forming step. (C) After removing the first and second Al films and diffusing first conductivity type impurities in the first trench to form a first conductivity type impurity layer as a channel stopper layer, And oxidizing the inside of the groove to form a SiO ₂ film on the surface of the first conductivity type impurity layer. (D) Using the CVD SiO ₂ film as a mask for ion implantation, diffusing second conductivity type impurities into the semiconductor substrate,
Forming a well of the second conductivity type in a region shallower than the trench. (E) Polysilicon is formed on the entire surface of the semiconductor substrate to fill the first trench, and then the polysilicon is anisotropically etched to form the CVDSiO ₂ film.
Forming polysilicon sidewalls that are located slightly inside both sides of the first trench in which both sidewalls of the film are filled with polysilicon. (F) a SiO ₂ film according 3Al film and ECR plasma method are sequentially formed on the entire surface of the semiconductor substrate, by wet-etching the SiO ₂ film by the ECR plasma method,
After opening windows on both sides of the sidewall, the ECR
A step of etching the third Al film in the window using the SiO ₂ film formed by the plasma method as a mask, and then removing the SiO ₂ film formed by the ECR plasma method. (G) A second groove is formed in a region partially overlapping the first groove by anisotropically etching the semiconductor substrate using the third Al film remaining on the semiconductor substrate as a mask. Process. (H) Impurities of the second conductivity type are diffused in the second groove to form a second conductivity type impurity layer as a channel stopper layer, and the second groove is oxidized to form the second conductivity. A step of forming a SiO ₂ film on the surface of the type impurity layer. (I) The third Al film, the sidewall, the CVDSiO
After removing the ₂ film and the Si ₃ N ₄ film, polysilicon is etched back to fill the second groove, and then an SiO ₂ film is formed on the surface of the polysilicon to form a groove-shaped isolator. Process to complete the ration.