KR970013428A - Polysilicon Thin Film Transistor Using Nitride Film as Gate Insulating Film and Manufacturing Method Thereof - Google Patents

Polysilicon Thin Film Transistor Using Nitride Film as Gate Insulating Film and Manufacturing Method Thereof Download PDF

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Publication number
KR970013428A
KR970013428A KR1019950028152A KR19950028152A KR970013428A KR 970013428 A KR970013428 A KR 970013428A KR 1019950028152 A KR1019950028152 A KR 1019950028152A KR 19950028152 A KR19950028152 A KR 19950028152A KR 970013428 A KR970013428 A KR 970013428A
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South Korea
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nitride film
pattern
impurity semiconductor
semiconductor layer
forming
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KR1019950028152A
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Korean (ko)
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KR100323736B1 (en
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장진
이경하
정유찬
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장진
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Priority to US09/057,538 priority patent/US6100119A/en
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Publication of KR100323736B1 publication Critical patent/KR100323736B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 질화막을 게이트 절연막으로 사용한 다결정실리콘 TFT 및 그 제조 방법에 관한 것으로 다결정실리콘 패턴상에 이온스토퍼가 되는 제1질화막 패턴을 형성하고, 고농도 이온 주입을 실시하여 다결정실리콘 패턴의 양측부에 고농도 불순물 반도체층을 형성하며, 상기 구조의 전표면에 층간절연막이 되는 제2질화막을 도포하고 소오스/드레인 콘택을 형성한 후, 금속으로 된 소오스/드레인 전극과 게이트 전극 패턴을 형성하여 TFT를 완성하였으므로, 게이트절연막을 저온에서 형성하여 채널과의 계면에 결함생성이 방지되고 고농도 불순물 반도체층 형성을 위한 이온 주입시 제1질화막 패턴이 이온스토퍼로 되어 양이온의 축적을 방지하므로 게이트절연막의 특성열화를 방지하여 소자 동작의 신뢰성을 향상시킬 수 있는 잇점이 있다.The present invention relates to a polysilicon TFT using a nitride film as a gate insulating film, and a method of manufacturing the same. A first nitride film pattern serving as an ion stopper is formed on a polysilicon pattern. After forming an impurity semiconductor layer, applying a second nitride film serving as an interlayer insulating film to the entire surface of the structure, forming a source / drain contact, and forming a source / drain electrode and a gate electrode pattern made of metal to complete the TFT. , The gate insulating film is formed at a low temperature to prevent defect formation at the interface with the channel, and the ionization pattern of the first nitride film becomes an ion stopper during ion implantation for the formation of a high concentration impurity semiconductor layer, thereby preventing the accumulation of cations, thereby preventing the deterioration of the characteristics of the gate insulating film. Therefore, there is an advantage in that the reliability of device operation can be improved.

Description

질화막을 게이트절연막으로 사용한 다결정실리콘 박막트랜지스터 및 그 제조방법Polysilicon Thin Film Transistor Using Nitride Film as Gate Insulating Film and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 새로운 박막트랜지스터의 단면도.3 is a cross-sectional view of a new thin film transistor according to the present invention.

Claims (3)

제1항, 절연기판상에 형성되어 있는 다결정실리콘 패턴과, 상기 다결정실리콘 패턴에서 채널로 예정되어 있는 부분상에 형성되어 있는 이온주입 마스크의 역할을 수행하는 제1질화막 패턴과, 상기 제1질화막 패턴 양측의 다결정실리콘 패턴 상부에 형성되어 있는 고농도 불순물 반도체층과, 상기 구조의 전표면에 형성되어 있는 층간절연막이 되는 제2질화막과, 상기 양측 고농도 불순물 반도체층 상부의 제2질화막이 제거되어 고농도 불순물 반도체층을 노출시키는 콘택홀과, 상기 콘택홀을 통하여 고농도 불순물 반도체층과 접촉되는 소오스/드레인 전극과, 상기 제1질화막 패턴 상측의 제2질화막상에 형성되어 있는 게이트전극을 구비하는 TFT의 제조방법.The first nitride film pattern serving as a polysilicon pattern formed on an insulating substrate, an ion implantation mask formed on a portion of the polycrystalline silicon pattern, which is defined as a channel, and the first nitride film. The high concentration impurity semiconductor layer formed on the polysilicon patterns on both sides of the pattern, the second nitride film serving as the interlayer insulating film formed on the entire surface of the structure, and the second nitride film on the both high concentration impurity semiconductor layers are removed to obtain high concentration. A TFT having a contact hole exposing an impurity semiconductor layer, a source / drain electrode contacting the high concentration impurity semiconductor layer through the contact hole, and a gate electrode formed on the second nitride film above the first nitride film pattern. Manufacturing method. 절연기판상에 다결정실리콘을 형성하는 공정과, 상기 다결정실리콘 패턴에서 채널로 예정되어 있는 부분상에 제1질화막 패턴 양측의 다결정실리콘 패턴 상부 표면에 고농도 불순물 반도체층을 형성하는 공정과, 상기 구조의 전표면에 제2질화막을 형성하는 공정과, 상기 고농도 불순물 반도체층 상부의 제2질화막을 제거하여 고농도 불순물 반도체층을 노출시키는 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 고농도 불순물 반도체층과 접촉되는 소오스/드레인 전극을 형성하는 공정과, 상기 제1질화막 패턴 상부의 제2질화막상에 게이트전극을 형성하는 공정을 구비하는 TFT의 제조방법.Forming polycrystalline silicon on an insulating substrate, forming a highly-concentrated impurity semiconductor layer on the upper surface of the polycrystalline silicon pattern on both sides of the first nitride film pattern on the portion of the polycrystalline silicon pattern intended as the channel; Forming a second nitride film on an entire surface, forming a contact hole exposing the high concentration impurity semiconductor layer by removing the second nitride film on the high concentration impurity semiconductor layer, and a high concentration impurity semiconductor layer through the contact hole; Forming a source / drain electrode in contact, and forming a gate electrode on the second nitride film on the first nitride film pattern. 다결정실리콘 TFT에서 다결정실리콘과 계면을 이루는 절연막을 플라즈마화학기상증착 방법에 의한 실리콘나이트라이드를 이용하는 TFT구조 및 절연막 제조방법.A TFT structure and an insulating film manufacturing method using silicon nitride by the plasma chemical vapor deposition method in the insulating film interfaced with the polycrystalline silicon in the polysilicon TFT. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950028152A 1995-08-31 1995-08-31 Thin film transistor and fabricating method thereof KR100323736B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950028152A KR100323736B1 (en) 1995-08-31 1995-08-31 Thin film transistor and fabricating method thereof
US09/057,538 US6100119A (en) 1995-08-31 1998-04-09 Thin film transistor and method for fabricating the same

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Application Number Priority Date Filing Date Title
KR1019950028152A KR100323736B1 (en) 1995-08-31 1995-08-31 Thin film transistor and fabricating method thereof

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JPH0442576A (en) * 1990-06-08 1992-02-13 Seiko Epson Corp Thin film transistor
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