KR970054191A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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KR970054191A
KR970054191A KR1019950064412A KR19950064412A KR970054191A KR 970054191 A KR970054191 A KR 970054191A KR 1019950064412 A KR1019950064412 A KR 1019950064412A KR 19950064412 A KR19950064412 A KR 19950064412A KR 970054191 A KR970054191 A KR 970054191A
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transistor
gate
channel layer
channel
layer pattern
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KR1019950064412A
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KR100219056B1 (en
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최진호
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 SRAM구조 및 그 제조방법에 관한 것으로, 공정에 의한 제약을 받지 않으면서 셀 비율을 증가시키기 위한 것이다.The present invention relates to an SRAM structure and a method of manufacturing the same, to increase the cell ratio without being constrained by the process.

이를 위해 본 발명은 각각이 체널층과, 상기 채널층 상부에 게이트절연막을 개재하여 형성되는 게이트와, 상기 게이트 양단의 상기 채널층 부분에 형성된 소오스 및 드레인으로 구성되는 구동 트랜지스터와 억세스 트랜지스터를 포함하는 반도체장치에 있어서, 상기 구동 트랜지스터의 채널층과 상기 억세스 트랜지스터의 채널층이 서로 두께가 다른 것을 특징으로 하는 반도체장치를 제공한다.To this end, the present invention includes a driving transistor and an access transistor each comprising a channel layer, a gate formed on the channel layer via a gate insulating film, and a source and a drain formed on the channel layer portion across the gate. A semiconductor device, wherein the channel layer of the driving transistor and the channel layer of the access transistor are different in thickness from each other.

Description

반도체장치 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1도는 본 발명의 일실시예에 의한 SRAM셀 제조방법을 도시한 공정순서도이고, 제2도는 본 발명의 다른 실시예에 의한 SRAM셀 제조방법을 도시한 공정순서도이다.1 is a process flow chart showing a SRAM cell manufacturing method according to an embodiment of the present invention, Figure 2 is a process flow chart showing a SRAM cell manufacturing method according to another embodiment of the present invention.

Claims (13)

각각이 채널층과, 상기 채널층 상부에 게이트절연막을 개재하여 형성되는 게이트와, 상기 게이트 양단의 상기 채널층 부분에 형성된 ㅗ오스 및 드레인으로 구성되는 구동 트랜지스터와 억세스 트랜지스터를 포함하는 반도체장치에 있어서, 상기 구동 트랜지스터의 채널층과 상기 억세스 트랜지스터의 채널층이 서로 두께가 다른 것을 특징으로 하는 반도체장치.10. A semiconductor device comprising: a driving transistor and an access transistor, each of which comprises a channel layer, a gate formed over the channel layer via a gate insulating film, and a pulse and drain formed in the channel layer portion across the gate. And a channel layer of the driving transistor and a channel layer of the access transistor have different thicknesses. 제1항에 있어서, 상기 구동 트랜지스터이 채널층이 상기 억세스 트랜지스터의 채널층보다 두꺼운 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the driving transistor has a channel layer thicker than that of the access transistor. 제 1항에 있어서, 상기 구동 트랜지스터의 소오스 및 드레인의 두께가 상기 억세스 트랜지스터의 소오스 및 드레인 두께보다 두꺼운 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the source and drain thicknesses of the driving transistors are thicker than the source and drain thicknesses of the access transistors. 제1항에 있어서, 상기 구동 트랜지스터의 채널층은 상기 게이트 하부의 채널영역이 그 양단의 소오스 및 드레인영역보다 얇은 형태로 이루어진 것을 특징으로 한느 반도체장치.The semiconductor device of claim 1, wherein the channel layer of the driving transistor is formed to have a channel region below the gate being thinner than the source and drain regions at both ends thereof. 제1항에 있어서, 상기 구동 트랜지스터의 채널층은 상기 게이트 하부의 채널영역이 그 양단의 소오스 및 드레인 영역보다 얇은 형태로 이루어지고, 상기 억세스 트랜지스터의 채널층은 상기 구동 트랜지스터의 채널층이 채널영역과 동이한 두께를 갖는 것을 특징으로 하는 반도체장치.The channel layer of the driving transistor has a channel region below the gate is thinner than the source and drain regions at both ends thereof, and the channel layer of the access transistor is a channel region of the driving transistor. It has a thickness similar to that of a semiconductor device. 제1항에 있어서, 상기 억세스 트랜지스터의 채널층은 상기 게이트 하부의 채널영역이 그 양단의 소오스 및 드레인 영역보다 얇은 형태로 이루어진 것을 특징으로 하는 반도체장치.The semiconductor device of claim 1, wherein the channel layer of the access transistor is formed to have a channel region below the gate being thinner than the source and drain regions at both ends thereof. 제1항에 있어서, 상기 억세스 트랜지스터의 채널층은 상기 게이트 하부의 채널영역이 그 양단의 소오스 및 드레인영역보다 얇은 형태로 이루어지고, 상기 구동 트랜지스터의 채널층은 상기 억세스 트랜지스터 채널층의 소오스 및 드레인영역과 동일한 두께를 갖는 것을 특징으로 하는 반도체장치.The channel layer of the access transistor has a channel region below the gate is thinner than the source and drain regions at both ends thereof, and the channel layer of the driving transistor is the source and drain of the access transistor channel layer. A semiconductor device having the same thickness as the region. 제1항에 있어서, 상기 채널층은 SOI로 이루어짐을 특징으로 하는 반도체장치.The semiconductor device of claim 1, wherein the channel layer is formed of SOI. 기판상에 형성된 절연막상에 SOI층을 형성하는 단계와, LOCOS공정을 통해 제1트랜지스터 및 제2트랜지스터의 각각의 채널층이 되는 SOI층 패턴을 형성하는 단계, 및 상기 제1트랜지스터의 SOI층 패턴의 두께를 상기 제2트랜지스터의 SOI층 패턴 두께보다 얇게 만드는 단계를 포함한 것을 특징으로 하는 반도체장치.Forming an SOI layer on an insulating film formed on the substrate, forming an SOI layer pattern that becomes a channel layer of each of the first transistor and the second transistor through a LOCOS process, and the SOI layer pattern of the first transistor And making the thickness of the second transistor smaller than the thickness of the SOI layer pattern of the second transistor. 제9항에 있어서, 상기 제1트랜지스터와 제2트랜지스터는 각각 SRAM셀의 억세스 트랜지스터와 구동 트랜지스터인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 9, wherein the first transistor and the second transistor are access transistors and driving transistors of an SRAM cell, respectively. 제 9항에 있어서, 상기 제1트랜지스터의 SOI층 패턴의 두께를 상기 제2트랜지스터의 SOI층 패턴 두께보다 얇게 만드는 단계는 LOCOS공정을 진행하여 상기 제2트랜지스터의 게이트가 형성될 SOI층 패턴 부분에 선택적으로 산화막을 형성함과 동시에 제1트랜지스터의 SOI층 패턴 전표면상에 산화막을 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체장치 제조방법.10. The method of claim 9, wherein the making the thickness of the SOI layer pattern of the first transistor smaller than the thickness of the SOI layer pattern of the second transistor is performed by a LOCOS process to a portion of the SOI layer pattern where the gate of the second transistor is to be formed. And selectively forming an oxide film and simultaneously forming an oxide film on the entire surface of the SOI layer pattern of the first transistor. 제 9항에 있어서, 상기 제1트랜지스터의 SOI층 패턴의 두께를 상기 제2트랜지스터의 SOI층 패턴 두께보다 얇게 만드는 단계는 LOCOS공정을 진행하여 상기 제1트랜지스터의 게이트가 형성될 SOI층 패턴 부분에 선택적으로 산화막을 형성하는 공정으로 이루어지는 것을 특징으로 하는 반도체장치 제조방법.10. The method of claim 9, wherein the step of making the thickness of the SOI layer pattern of the first transistor smaller than the thickness of the SOI layer pattern of the second transistor is performed by a LOCOS process to a portion of the SOI layer pattern where the gate of the first transistor is to be formed. And a step of selectively forming an oxide film. 제 9항에 있어서, 상기 제1트랜지스터의 SOI층 패턴의 두께를 상기 제2트랜지스터의 SOI층 패턴 두께보다 얇게 만드는 단계후에 채널 이온주입을 행하는 단계, 상기 제1트랜지스터 및 제2트랜지스터 각각 SOI층 패턴 전면에 게이트산화막을 형성하는 단계, 상기 게이트산화막 상부 소정영역에 제1트랜지스터의 게이트 및 제2트랜지스터의 게이트를 각각 형성하는 단께, 이온주입을 행하여 상기 ZOI층 패턴 소정영역에 제1트랜지스터 및 제2트랜지스터 각각이 소오스 및 드레인영역을 형성하는 단계, 기판 전면에 절연층을 형성하는 단계, 상기 절연층을 선택적으로 식각하여 제1트랜지스터와 제2트랜지스터 각각의 소오스 및 드레인영역을 노출 시키는 콘택홀을 형성하는 단계, 및 상기 콘택홀을 통해 제1 및 제2트랜지스터 각각의 소오스 및 드레인 영역에 접속되는 금속배선을 상기 절연층상에 형성하는 단계가 더 포함되는 것을 특징으로 하는 반도체장치 제조방법.10. The method of claim 9, wherein the channel ion implantation is performed after making the thickness of the SOI layer pattern of the first transistor smaller than the thickness of the SOI layer pattern of the second transistor, wherein the SOI layer pattern of each of the first transistor and the second transistor is performed. Forming a gate oxide film on the entire surface, forming a gate of a first transistor and a gate of a second transistor in a predetermined region of the gate oxide film, and ion implantation to perform a first transistor and a second transistor in a predetermined region of the ZOI layer pattern; Forming a source and drain region of each transistor, forming an insulating layer on the entire surface of the substrate, and selectively etching the insulating layer to form contact holes exposing the source and drain regions of each of the first and second transistors. And contacting the source and drain regions of each of the first and second transistors through the contact hole. How the metal wires to a semiconductor manufacturing apparatus characterized in that further includes the step of forming the insulating layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950064412A 1995-12-29 1995-12-29 A semiconductor device and fabrication method of the same KR100219056B1 (en)

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