KR970003682A - MOS transistor manufacturing method with low doped drain structure - Google Patents

MOS transistor manufacturing method with low doped drain structure Download PDF

Info

Publication number
KR970003682A
KR970003682A KR1019950015098A KR19950015098A KR970003682A KR 970003682 A KR970003682 A KR 970003682A KR 1019950015098 A KR1019950015098 A KR 1019950015098A KR 19950015098 A KR19950015098 A KR 19950015098A KR 970003682 A KR970003682 A KR 970003682A
Authority
KR
South Korea
Prior art keywords
nitride film
drain structure
depositing
etching
mos transistor
Prior art date
Application number
KR1019950015098A
Other languages
Korean (ko)
Other versions
KR100197521B1 (en
Inventor
김천수
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950015098A priority Critical patent/KR100197521B1/en
Publication of KR970003682A publication Critical patent/KR970003682A/en
Application granted granted Critical
Publication of KR100197521B1 publication Critical patent/KR100197521B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

고집적 반도체 소자 제조 방법.Highly integrated semiconductor device manufacturing method.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

소자가 고집적화됨에 따라 이온주입의 영향으로 게이트 오후버랩 부분을 정확히 제어하는 것이 어려워 펀치쓰로우 효과,쉐도우 효과 및 채널링 효과등이 생겨 소자의 신뢰성이 떨어지고 소자의 수명도 짧아진다는 문제점을 해결하고자 함.As the device is highly integrated, it is difficult to accurately control the gate afternoon bubble part due to the ion implantation, resulting in a punch-through effect, shadow effect, and channeling effect. .

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

게이트용 폴리실리콘 위에 질화막을 증착하고 종래 산화막을 측벽스페이서로 이용하는 방법 대신 질화막을 이용하므로서써, 게이트 오버랩부분을 정확히 제어할 수 있고 쉐도우 효과 및 채널링 효과를 방지한 저도핑 드레인 구조의 모스 트랜지스터를 제조하고자 함.By using a nitride film instead of depositing a nitride film on the gate polysilicon and using a conventional oxide film as a sidewall spacer, a MOS transistor having a low doping drain structure can be precisely controlled and a shadow effect and a channeling effect are prevented. To do so.

4. 발명의 중요한 용도4. Important uses of the invention

저도핑 드레인 구조의 모스 트랜지스터 제조에 이용됨.Used to manufacture MOS transistors with low doped drain structure.

Description

저도핑 드레인 구조의 모스 트랜지스터 제조 방법MOS transistor manufacturing method with low doped drain structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1G도는 본 발명의 저도핑 드레인 구조의 모스(MOS) 트랜지스터 제조 방법에 따른 공정도.1A to 1G are process drawings according to the MOS transistor manufacturing method of the low doped drain structure of the present invention.

Claims (5)

저도핑 드레인 구조의 모스 트랜지스터를 제조하는 방법에 있어서, 웰이 형성된 반도체 기판 상에 게이트산화막을 성장시킨 후 게이트 전극용 폴리실리콘을 증착하는 단계와, 질화막의 증착을 용이하게 하기 위한 완충막을 성장시킨 후 질화막을 증착하는 단계와, 채널 영역이 형성될 부위만 포토레지스트가 잔류하도록 포토레지스트 패턴을 형성한후 상기 포토레지스트 패턴을 식각 배리어로 이용하여 상기 질화막과 완충막층을 식각하는 단계와, 저도핑 이온 주입을실시하고 어닐링을 실시하는 단계와, 스페이서용 질화막을 증착하고 블랭킷 식각을 실시하여 질화막 측벽 스페이서를 형성하는 단계와, 상기 질화막 측벽 스페이서와 질화막을 식각 베리어로 이용하여 상기 게이트용 폴리실리콘 식각하여 게이트 전극을 형성하는 단계와, 상기 완충막과 질화막을 제거한 후, 이온주입을 실시하여 소스/드레인 영역을 형성하는 단계및 스페이서용 산화막을 증착하고 블랭킷 식각을 실시하여 측벽 스페이서를 형성하는 단계를 포함해서 이루어진 저도핑드레인 구조의 모스 트렌지스터 제조 방법.A method of manufacturing a MOS transistor having a low doped drain structure, comprising: growing a gate oxide film on a well formed semiconductor substrate and depositing polysilicon for a gate electrode; and growing a buffer film to facilitate deposition of the nitride film. Depositing a nitride film, forming a photoresist pattern such that only a portion of the channel region is formed therein, and then etching the nitride film and the buffer layer using the photoresist pattern as an etch barrier, and low doping Performing ion implantation and annealing, depositing a spacer nitride film and performing blanket etching to form a nitride film sidewall spacer, and etching the gate polysilicon using the nitride film sidewall spacer and the nitride film as an etching barrier. Forming a gate electrode, and the buffer layer After removing the nitride film, by conducting an ion implantation process for producing the source / depositing step and the spacer oxide film for forming the drain region, and by carrying out a blanket etching of I Ping drain structure made by forming a sidewall spacer MOS transistor. 제1항에 있어서, 상기 완충막층은 테트라-에틸-오소-실리케이트로 이루어진 것을 특징으로 하는 저도핑 드레인 구조의 모스 트랜지스터 제조방법.The method of claim 1, wherein the buffer layer is made of tetra-ethyl-oso-silicate. 제1항 또는 제2항에 있어서, 상기 완충막층의 두께는 약 200Å인 것을 특징으로 하는 저도핑 드레인 구조의 모스 트랜지스터 제조 방법.The method of claim 1 or 2, wherein the buffer layer has a thickness of about 200 GPa. 제1항에 있어서, 상기 저도핑 드레인 이온 주입은 1×1014㎝-2의 인이온을 150keV 의 에너지를 가해 실시하는 것을 특징으로 하는 저도핑 드레인 구조의 모스 트랜지스터 제조 방법.The method of claim 1, wherein the low doping drain ion implantation is performed by applying a 150 kV energy to phosphorus ion of 1 × 10 14 cm −2 . 제1항에 있어서, 상기 어닐링 공정은 약 850℃의 온도에서 약 30분간 수행되는 것을 특징으로 하는 저도핑드레인 구조의 모스 트랜지스터 제조 방법.The method of claim 1, wherein the annealing process is performed at a temperature of about 850 ° C. for about 30 minutes. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950015098A 1995-06-05 1995-06-05 Method for manufacturing mosfet of low-doping drain structure KR100197521B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950015098A KR100197521B1 (en) 1995-06-05 1995-06-05 Method for manufacturing mosfet of low-doping drain structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950015098A KR100197521B1 (en) 1995-06-05 1995-06-05 Method for manufacturing mosfet of low-doping drain structure

Publications (2)

Publication Number Publication Date
KR970003682A true KR970003682A (en) 1997-01-28
KR100197521B1 KR100197521B1 (en) 1999-06-15

Family

ID=19416699

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950015098A KR100197521B1 (en) 1995-06-05 1995-06-05 Method for manufacturing mosfet of low-doping drain structure

Country Status (1)

Country Link
KR (1) KR100197521B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100361529B1 (en) * 1995-12-29 2003-08-21 Hynix Semiconductor Inc Method for manufacturing mos transistor with lightly doped drain structure
KR100451318B1 (en) * 1997-12-26 2004-11-26 주식회사 하이닉스반도체 Semiconductor fabrication method for enhancing reliability by minimizing channeling phenomenon in ion implantation process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100361529B1 (en) * 1995-12-29 2003-08-21 Hynix Semiconductor Inc Method for manufacturing mos transistor with lightly doped drain structure
KR100451318B1 (en) * 1997-12-26 2004-11-26 주식회사 하이닉스반도체 Semiconductor fabrication method for enhancing reliability by minimizing channeling phenomenon in ion implantation process

Also Published As

Publication number Publication date
KR100197521B1 (en) 1999-06-15

Similar Documents

Publication Publication Date Title
KR20000068441A (en) Asymmetrical transist0r with lightly and heavily doped drain regions and ultra-heavily doped source region
KR940016938A (en) MOS transistor and its manufacturing method
KR970003682A (en) MOS transistor manufacturing method with low doped drain structure
KR100336771B1 (en) Transistor forming method
KR960035912A (en) Transistor manufacturing method of semiconductor device
JPH0472770A (en) Manufacture of semiconductor device
KR100219073B1 (en) Mosfet and method of manufacturing the same
KR100438666B1 (en) Method for manufacturing field effect transistor using photoresist spacer as ion-implantation mask of ldd structure
KR100307540B1 (en) Fabricating method of semiconductor device
KR970003447A (en) Annealing method of source / drain regions of MOS transistors
KR970054398A (en) Most transistor manufacturing method
KR950021269A (en) Source / Drain Formation Method of Semiconductor Device
KR970054501A (en) Low doping drain thin film transistor manufacturing method
KR950009978A (en) Manufacturing method of morph transistor
KR970013120A (en) Thin film transistor and method of manufacturing the same
JPH05267600A (en) Manufacture of semiconductor device
KR950034669A (en) Manufacturing method of semiconductor device
KR960036021A (en) MOS transistor manufacturing method with low doped drain structure
KR940016929A (en) MOS transistor manufacturing method
KR960043290A (en) Thin film transistor with double gate electrode structure and manufacturing method thereof
KR960035926A (en) Low doping drain thin film transistor manufacturing method
KR960026972A (en) Low Doping Drain (LDD) Thin Film Transistor and Manufacturing Method Thereof
KR970053077A (en) Semiconductor device manufacturing method
KR910001902A (en) Method for forming lightweight doped drain source of gate electrode film in MOS transistor
KR970054392A (en) Transistor manufacturing method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100126

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee