JPH05267600A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the diffusion of boron to a gate insulating layer and crystal layer by activating n-type impurity ion-implanted in a second semiconductor layer, by subjecting a semiconductor and thin film to a surface treatment for introducing p-type impurity in the thin film into the semiconductor layer of a first region through diffusion and thereafter by selectively removing the thin film. CONSTITUTION:After a gate insulating layer 5 is formed on the semiconductor crystal surfaces of MIS-FET forming region 4 having p-type gate and MIS-FET forming region 3 having n-type gate, a polysilicon layer 7 is deposited on the surfaces. Then, the thin film 10 of glass silicate containing boron is formed so as to cover the region 3 and to expose the region 4. After n-type impurity is ion-implanted in the exposed surface of the polysilicon layer 7 by the use of the thin film as mask, the thin film 10 and polysilicon layer 7 are subjected to surface treatment so that the boron in the thin film 10 is subjected to solid- phase diffusion and the n-type impurity in the polysilicon layer 7 is activated. After that, the thin film 10 is removed and the polysilicon layer 7 is patterned on gate electrodes 71, 72.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor (MOS- or MIS-FET), and more particularly to a complementary field effect transistor (CMOS-FET or CMIS-FET).
The method of forming an electrode of

[0002]

2. Description of the Related Art With the recent increase in density of semiconductor integrated circuits, it is required to reduce the channel length of MIS-FET. However, the so-called short-channel effect, in which the breakdown voltage and the threshold voltage decrease, becomes remarkable as the channel length decreases. As a method of preventing such a short channel effect, a gate electrode has recently been formed of a semiconductor having the same conductivity type as the channel. This is to avoid the buried channel type, which is apt to cause substrate punch-through, and to use the surface channel type, which is particularly effective for p-type MIS-FET.

[0003]

Conventionally, in order to reduce the resistance of a gate electrode made of polysilicon, doping with impurities has been performed. In order to form the gate electrode as described above, it is necessary to introduce impurities of different conductivity types depending on the conductivity type of the channel. Conventionally, MIS-FETs with n-type channels have been Arsenic (As) or phosphorus (P) is ion-implanted into the silicon layer, while the MIS-FET with p-type channel is
It was formed by ion-implanting boron (B) into polysilicon. However, in order to reduce the resistance of each gate electrode, if the ion implantation amount of impurities is increased, especially in the p-channel MIS-FET, boron is added.
(B) has been doped into the semiconductor crystals in the gate insulating layer and channel region, resulting in MIS-FE with desired characteristics.
There was a problem that T could not be formed.

The doping of boron (B) into the gate insulating layer and the channel region as described above means that the boron (B) ion-implanted into the polysilicon layer diffuses into the gate insulating layer in the subsequent heat treatment step, and This is because it penetrates through the insulating layer and reaches the underlying semiconductor crystal. N-type impurities such as arsenic (As) and phosphorus (P) do not diffuse as easily as boron (B), and therefore do not have a significant effect.

The present invention provides a method capable of introducing a high concentration of boron (B) into a polysilicon layer forming a gate electrode of a p-channel MIS-FET without causing the above problems. The purpose is to do.

[0006]

The above object is to provide a first region in which an insulated gate field effect transistor having a p-type channel is formed and a second region in which an insulated gate field effect transistor having an n-type channel is formed. A gate insulating layer is formed on one surface of the semiconductor substrate having a region defined therein, an undoped semiconductor layer is formed on the surface of the semiconductor substrate on which the gate insulating layer is formed, and a p-type impurity is included. A thin film made of a material that is selectively removable with respect to the semiconductor layer and having a thickness that serves as a mask in ion implantation is formed on the semiconductor layer, and the thin film is left in at least the first region and the first region is formed. Patterning so as to be removed from the second region, ion-implanting n-type impurities into the semiconductor layer in the second region using the patterned thin film as a mask, A surface heat treatment for activating the n-type impurities ion-implanted into the semiconductor layer in the region and introducing the p-type impurity in the thin film into the semiconductor layer in the first region by diffusion. The present invention is achieved by a method for manufacturing a semiconductor device according to the present invention, which includes various steps of applying to a semiconductor layer and a thin film and then selectively removing the thin film.

[0007]

In the present invention, boron (B) which is a p-type impurity
Is a silicate glass (BSG) containing, for example, boron (B) formed on the polysilicon layer for forming the gate electrode.
It is supplied by solid phase diffusion with the layer as the diffusion source. On the other hand, n
The n-type impurities such as arsenic (As) to the polysilicon layer for forming the gate electrode of the p-channel MIS-FET are introduced by ion implantation. In this ion implantation, the p-channel MIS-FET formation region is formed. The above BSG layer is used as a mask for. The diffusion of boron (B) from the BSG layer to the polysilicon layer and the activation of arsenic (As) ion-implanted into the polysilicon layer are performed by infrared irradiation, for example.
By using RTA (rapid thermal annealing) to selectively heat the surface of the BSG layer or polysilicon layer in a short time, it is possible to remove boron (B) in the gate insulating layer or crystal layer. Diffusion is prevented. In addition, JP-A-54-3
In 0784, for the purpose of simplifying the process of manufacturing a complementary MOS-FET formed by forming a p-channel MOS-FET and an n-channel MOS-FET in an island-shaped epitaxial layer on an insulating substrate, As a n-type impurity to be introduced into the source / drain region and the polysilicon gate electrode by depositing phosphosilicate glass (PSG) in the region where the channel-type MOS-FET is formed,
A method of diffusing phosphorus (P) in the PSG film is disclosed. However, this method is not intended to solve the problem caused by the diffusion of boron (B) ion-implanted as a p-type impurity as in the present invention, and therefore the surface heat treatment of the PSG film, which is the impurity diffusion source, is not performed. It is not essential, and there is also a process difference in that the PSG film is deposited after patterning the polysilicon gate electrode.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of an essential part for explaining a process of one embodiment of the present invention. As shown in FIG. 1 (a), a predetermined region of a semiconductor substrate 1 made of, for example, p-type silicon. Then, the isolation insulating layer 2 is formed by the well-known LOCOS (local oxidation of silicon) method. By introducing impurities of a predetermined conductivity type into the element regions defined by the isolation insulating layer 2, n
After forming the wells 3 and p-type well 4, the surfaces of the wells 3 and 4 are thermally oxidized to form the gate insulating layer 5. The n-type well 3 and the p-type well 4 are, for example,
Arranged to be convenient for constructing the CMIS-FET.
The above is the same as the usual process. Note that reference numeral 6 is a channel cut made of p-type impurities previously introduced into the surface of the semiconductor substrate 1 before the formation of the isolation insulating layer 2.

Next, for example, well-known CVD (chemical vapor deposition)
By the method, a semiconductor layer 7 made of polysilicon not doped with impurities and having a thickness of about 0.1 to 0.3 μm is deposited on the entire surface of the semiconductor substrate 1.

Then, as shown in FIG. 1 (b), for example, a silicate glass (BSG) containing boron (B) or an organic compound containing boron (B) called polyboron film (PBF) is used. The thin film 10 is formed on the semiconductor layer 7. The BSG thin film is applied by the well-known CVD method, and the PBF is applied by a solution of the above organic compound (for example, product number PBF-31 manufactured by Tokyo Ohka Co., Ltd.) by spin coating. Since the thin film 10 is also used as a mask in the ion implantation described later,
It is necessary to have a thickness of about 2 to 0.4 μm.

Then, as shown in FIG. 1 (c), the well 3
The thin film 10 is patterned so as to cover the wells and expose the wells 4. The patterning of the thin film 10 made of BSG or PBF may be performed using, for example, a resist mask and RIE (reactive ion etching) using CHF ₃ as an etchant. After that, arsenic (As) or phosphorus (P) is ion-implanted into the semiconductor layer 7 using the thin film 10 as a mask.
This ion implantation condition is, for example, an ion energy of 20
It is 40 KeV and the dose amount is 1 to 5 × 10 ¹⁵ pieces / cm ² .

Next, the surface of the thin film 10 and the semiconductor layer 7 is heat-treated by, for example, a so-called RTA (rapid thermal annealing) method using infrared irradiation. This heat treatment is a thin film
It is sufficient to heat the semiconductor layer 10 and the semiconductor layer 7 to 900 to 1000 ° C. for a short time of about several tens of seconds. By the above heat treatment, high-concentration boron (B) is uniformly diffused from the thin film 10 to the semiconductor layer 7 in contact therewith, while the arsenic (As) ion-implanted in the semiconductor layer 7 on the well 4 is activated. Be converted. According to the RTA, the boron (B) diffused in the semiconductor layer 7 does not diffuse further into the gate insulating layer 5 and further into the well 3.

Next, after selectively removing the thin film 10,
For example, by the CVD method, the thickness of SiO _{2 is} 0.1 to 0.3 μm.
The insulating layer was deposited on the insulating layer, as shown in Fig. 1 (d).
11 and the semiconductor layer 7 are patterned to form gate electrodes 71 and 72. By introducing impurities into the semiconductor layer 7, the gate electrode 71 becomes p-type and the gate electrode 72 becomes n-type. The thin film 10 may be removed by the same method as the patterning described with reference to FIG. The insulating layer 11 is formed for the purpose of surface protection and is not essential to the present invention.

Then, as shown in FIG.
As shown in (e), steps such as forming an LDD (lightly doped drain) region 12 and forming a sidewall insulating layer 13 are performed. That is,
With the well 3 covered with a resist mask (not shown), the gate electrode 72 is used as a mask to ion-implant a low-concentration n-type impurity into the well 4 to form an LDD 12, and then an insulating layer is deposited and etched back by RIE. Then, the sidewall insulating layer 13 is formed. Further, a resist mask not shown is used, and the gate electrodes 71 and 72 and the sidewall insulating layer 13 are used.
Using and as a mask, a high-concentration p-type impurity is added to the well 3.
High-concentration n-type impurities are ion-implanted into the well 4 to form p-type source / drain 15 and n-type source / drain 16. As a result, well 3 has a p-type channel.
An MIS-FET and an n-type channel MIS-FET of LDD structure are formed in the well 4, respectively.

After that, an interlayer insulating layer covering the entire surface of the semiconductor substrate 1 was formed, and contact holes (none of which were shown) for exposing the gate electrodes 71 and 72 and the source / drain 15 and 16, respectively, were formed therein. After that, wirings (not shown) connected to the gate electrodes 71 and 72 and the source / drain 15 and 16 through these contact holes are formed to complete the semiconductor device of the present invention. The gate electrodes 71 and 72 of the p-type channel MIS-FET formed in the well 3 and the n-type channel MIS-FET formed in the well 4 are interconnected, and one of the p-type source / drain 15 and the n-type source are connected. -By patterning the above wiring so that it is connected to one of the drains 16, a complementary MIS-FET is formed.

FIG. 2 is a sectional view of an essential part for explaining a process of another embodiment of the present invention, which is a fully depleted SOI (silico)
This is a case of forming a CMIS-FET having a structure of (on insulator). That is, an n-type channel MIS having a gate electrode 23 made of a p-type polysilicon layer in the same manner as in the above-mentioned embodiment on a semiconductor crystal 22 having a thickness of about 0.1 μm formed on a supporting substrate 20 via an insulating layer 21. Forming an FET and a p-type channel MIS-FET having a gate electrode 24 made of an n-type polysilicon layer. In the case of the present embodiment, the combination of the conductivity type of the gate electrodes 23 and 24 and the conductivity type of the wells 25 and 26 is different from that of the above embodiment, but a thin film made of BSG or BPF is used.
P-type gate electrode by solid-phase diffusion method using p-type impurity source
23, and the n-type gate electrode 24 is formed by ion-implanting n-type impurities using the thin film made of BSG or BPG as a mask, which is the same as the above-mentioned embodiment.

In the case of this embodiment, the semiconductor crystal 22
Is thin as described above, and the bottoms of the wells 25 and 26 and the bottoms of the n-type source / drain 27 and the p-type source / drain 28 reach the insulating layer 21.
The channel region of is completely depleted. Where n
The gate electrode 23 of the type channel MIS-FET is p-type, while
By making the gate electrode 24 of the p-type channel MIS-FET n-type, it becomes easy to make the absolute values of the threshold voltages of the CMIS-FET uniform.

[0018]

According to the present invention, boron is used as a p-type impurity.
It is possible to avoid undesired diffusion of boron (B) into the gate insulating layer and the underlying semiconductor crystal layer when (B) is ion-implanted into the gate electrode. As a result, the deterioration of the characteristics of the MIS-FET due to the introduction of impurities into the gate electrode to prevent the short channel effect, and the restrictions on the impurity concentration for reducing the resistance of the gate electrode are eliminated. It has an effect of contributing to the promotion of practical use of the semiconductor integrated circuit including the MIS-FET or CMIS-FET.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a second embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 12 LDD 2 isolation insulating layer 13 sidewall insulating layer 3, 4, 25, 26 well 15, 28 p-type source
Drain 5 Gate insulating layer 16, 27 n-type source
Drain 6 Channel cut 20 Support substrate 7 Semiconductor layer 22 Semiconductor crystal 10 Thin film 23, 24, 71, 72 Gate electrode 11, 21 Insulation layer

Claims (6)

[Claims] 1. A semiconductor substrate in which a first region in which an insulated gate field effect transistor having a p-type channel is formed and a second region in which an insulated gate field effect transistor having an n-type channel is formed are defined. A step of forming a gate insulating layer on one surface, a step of forming a semiconductor layer not doped with impurities on the surface of the semiconductor substrate on which the gate insulating layer is formed, and a step of forming a semiconductor layer containing p-type impurities Forming a thin film on the semiconductor layer, the thin film being made of a material that can be selectively removed with respect to, and having a thickness that serves as a mask in ion implantation, and leaving the thin film in at least the first region and the second region. Patterning so as to be removed from the region, and ion-implanting an n-type impurity into the semiconductor layer in the second region using the patterned thin film as a mask And activating the n-type impurity ion-implanted into the semiconductor layer in the second region and introducing the p-type impurity in the thin film into the semiconductor layer in the first region by diffusion. And a step of selectively removing the thin film after subjecting the semiconductor layer and the thin film to a surface heat treatment. 2. A gate electrode of a complementary field effect transistor, wherein the semiconductor layer in which the p-type impurity is introduced in the first region and the semiconductor layer in which the n-type impurity in the second region is ion-implanted are respectively used as gate electrodes of complementary field effect transistors. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of patterning. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming the semiconductor substrate on one surface of another supporting substrate via an insulating layer. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the thin film is formed by vapor-depositing silicate glass containing boron on the semiconductor layer. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the thin film is formed by applying an organic compound solution containing boron on the semiconductor layer. 6. The semiconductor according to claim 1, wherein the heat treatment is performed by irradiating the surface of the semiconductor substrate with infrared rays for a period of time in which p-type impurities in the thin film do not pass through the gate insulating layer. Device manufacturing method.