KR970054398A - Most transistor manufacturing method - Google Patents

Most transistor manufacturing method Download PDF

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Publication number
KR970054398A
KR970054398A KR1019950064436A KR19950064436A KR970054398A KR 970054398 A KR970054398 A KR 970054398A KR 1019950064436 A KR1019950064436 A KR 1019950064436A KR 19950064436 A KR19950064436 A KR 19950064436A KR 970054398 A KR970054398 A KR 970054398A
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KR
South Korea
Prior art keywords
gate
insulating film
gate insulating
impurities
forming
Prior art date
Application number
KR1019950064436A
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Korean (ko)
Inventor
김천수
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950064436A priority Critical patent/KR970054398A/en
Publication of KR970054398A publication Critical patent/KR970054398A/en

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 기판의 표면 소정 부위에 선택 이온주입 공정으로 저농도의 불순물 영역을 형성하는 단계; 상기 반도체 기판 상에 게이트 절연막 및 게이트 전도막을 차례로 형성하는 단계; 질소 이온을 전면 이온 주입하여 상기 게이트 절연막을 질화시키는 단계; 게이트 마스크를 사용하여 상기 게이트 전도막 및 게이트 절연막을 패터닝하고, 상기 패터닝된 게이트 절연막 측벽에 스페이서를 형성하는 단계; 고농도 불순물을 이온주입하고 열처리하여 소오스/드레인 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 모스트랜지스터 제조 방법에 관한 것으로, 질소 이온주입에 의해 게이트 산화막은 질화시켜 질화된 산화막(nitrided oxide)을 게이트 절연막으로 사용함으로써 게이트 전극에 높은 농도의 불순물이 도핑되더라도 이 불순물이 게이트 산화막을 열화시키지 않도록 함으로써 핫 캐리어 효과 및 숏채널 효과를 개선하여 소자의 특성을 개선한다.The present invention comprises the steps of forming a low concentration impurity region in a predetermined ion implantation process on a predetermined surface of the semiconductor substrate; Sequentially forming a gate insulating film and a gate conductive film on the semiconductor substrate; Nitriding the gate insulating layer by implanting nitrogen ions into the front surface; Patterning the gate conductive film and the gate insulating film using a gate mask, and forming spacers on sidewalls of the patterned gate insulating film; A method of manufacturing a MOS transistor, comprising: ion implanting a high concentration of impurities and performing a heat treatment to form a source / drain region. By using it as an insulating film, even if a high concentration of impurities are doped in the gate electrode, the impurities do not deteriorate the gate oxide film, thereby improving the hot carrier effect and the short channel effect, thereby improving device characteristics.

Description

모스트랜지스터 제조 방법Most transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제4도는 본 발명의 일실시예에 따른 모스트랜지스터 제조 공정도.1 to 4 is a process diagram for manufacturing a MOS transistor according to an embodiment of the present invention.

Claims (2)

모스트랜지스터 제조 방법 반도체 기판의 표면 소정 부위에 선택 이온주입 공정으로 저농도의 불순물 영역을 형성하는 단계; 상기 반도체 기판 상에 게이트 절연막 및 게이트 전도막을 차례로 형성하는 단계; 질소 이온을 전면 이온 주입하여 상기 게이트 절연막을 질화시키는 단계; 게이트 마스크를 사용하여 상기 게이트 전도막 및 게이트 절연막을 패터닝하고, 상기 패터닝된 게이트 절연막 측벽에 스페이서를 형성하는 단계; 고농도 불순물을 이온주입하고 열처리하여 소오스/드레인 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 모스트랜지스터 제조 방법.Forming a low concentration impurity region by a selective ion implantation process on a predetermined surface of a semiconductor substrate; Sequentially forming a gate insulating film and a gate conductive film on the semiconductor substrate; Nitriding the gate insulating layer by implanting nitrogen ions into the front surface; Patterning the gate conductive film and the gate insulating film using a gate mask, and forming spacers on sidewalls of the patterned gate insulating film; And implanting a high concentration of impurities and performing heat treatment to form a source / drain region. 제1항에 있어서, 상기 스페이서는 TEOS인 것을 특징으로 하는 모스트랜지스터 제조 방법.The method of claim 1, wherein the spacer is TEOS. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950064436A 1995-12-29 1995-12-29 Most transistor manufacturing method KR970054398A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950064436A KR970054398A (en) 1995-12-29 1995-12-29 Most transistor manufacturing method

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Application Number Priority Date Filing Date Title
KR1019950064436A KR970054398A (en) 1995-12-29 1995-12-29 Most transistor manufacturing method

Publications (1)

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KR970054398A true KR970054398A (en) 1997-07-31

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KR1019950064436A KR970054398A (en) 1995-12-29 1995-12-29 Most transistor manufacturing method

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100513064B1 (en) * 1998-12-30 2005-10-26 주식회사 하이닉스반도체 How to form a gate electrode of a transistor
KR100720405B1 (en) * 2001-12-28 2007-05-22 매그나칩 반도체 유한회사 Method for manufacturing of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100513064B1 (en) * 1998-12-30 2005-10-26 주식회사 하이닉스반도체 How to form a gate electrode of a transistor
KR100720405B1 (en) * 2001-12-28 2007-05-22 매그나칩 반도체 유한회사 Method for manufacturing of semiconductor device

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