KR950026029A - MOS transistor semiconductor device and manufacturing method thereof - Google Patents

MOS transistor semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
KR950026029A
KR950026029A KR1019940002183A KR19940002183A KR950026029A KR 950026029 A KR950026029 A KR 950026029A KR 1019940002183 A KR1019940002183 A KR 1019940002183A KR 19940002183 A KR19940002183 A KR 19940002183A KR 950026029 A KR950026029 A KR 950026029A
Authority
KR
South Korea
Prior art keywords
gate insulating
insulating layer
amorphous silicon
forming
mos transistor
Prior art date
Application number
KR1019940002183A
Other languages
Korean (ko)
Other versions
KR0137901B1 (en
Inventor
황현상
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940002183A priority Critical patent/KR0137901B1/en
Publication of KR950026029A publication Critical patent/KR950026029A/en
Application granted granted Critical
Publication of KR0137901B1 publication Critical patent/KR0137901B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

P+게이트를 갖는 PMOS 트랜지스터의 보론침투를 효과적으로 방지하도록 게이트 절연층과 게이트전극간에 질소가 포함된 비정질실리콘층을 개재한 MOS트랜지스터의 형성은 반도체 기판상에 게이트 절연층을 형성하는 단계와, 상기 게이트 절연층상에 박막의 비정질 실리콘층을 형성하고, 질소를 갖는 가스분위기에서 열처리하는 단계와, 게이트를 형성하기 위한 폴리실리콘층을 형성하고 이에 불순물을 도핑시키는 단계를 포함하며, 상기 공정에서 반도체 기판상에 게이트 절연층을 형성하는 단계후에 상기 게이트 절연층상에 박막의 비정질 실리콘층을 형성하고, 질소이온 비정질 실리콘층에 주입하는 단계로 열처리를 대신하는 공정이 또한 제공된다. 본 장치는 반도체 기판상에 형성된 게이트절연층과, 게이트 절연층위에 패턴 형성된 불순물원소를 포함하는 게이트전극과, 게이트 절연층 및 상기 게이트전극간에 형성된 박막의 질소를 함유하는 비정질실리콘층과, 게이트를 중심으로 기판영역내에 형성된 드레인, 소오스영역으로 구성되는 것을 특징으로 한다.Forming a MOS transistor via an amorphous silicon layer containing nitrogen between the gate insulating layer and the gate electrode to effectively prevent boron penetration of the PMOS transistor having a P + gate comprises forming a gate insulating layer on the semiconductor substrate, and Forming a thin amorphous silicon layer on the gate insulating layer, heat-treating in a gas atmosphere with nitrogen, and forming a polysilicon layer for forming the gate and doping impurities therein, wherein the semiconductor substrate is There is also provided a process of forming a thin film of amorphous silicon layer on the gate insulating layer after the step of forming a gate insulating layer on it, and injecting the nitrogen ion amorphous silicon layer in place of the heat treatment. The apparatus comprises a gate insulating layer formed on a semiconductor substrate, a gate electrode including a patterned impurity element on the gate insulating layer, an amorphous silicon layer containing nitrogen of a gate insulating layer and a thin film formed between the gate electrode, and a gate. And a drain and a source region formed in the substrate region.

Description

MOS트랜지스터 반도체 장치 및 그의 제조방법MOS transistor semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

첨부된 도면은 열처리온도에 따른 문턱전압의 변동 및 보론의 침투량을 종래와 본 발명에 대해 비교한 그래프이다.The accompanying drawings are graphs comparing the variation of threshold voltage and boron penetration according to the heat treatment temperature with respect to the conventional and the present invention.

Claims (13)

MOS트랜지스터의 제조방법에 있어서, 반도체 기판상에 게이트 절연층을 형성하는 단계와, 상기 게이트 절연층상에 박막의 비정질 실리콘층을 형성하고, 질소를 갖는 가스분위기에서 열처리하는 단계와, 게이트를 형성하기 위한 폴리실리콘층을 형성하고 이에 불순물을 도핑시키는 단계를 포함하는 것을 특징으로 하는 MOS 트랜지스터의 제조방법.A method of manufacturing a MOS transistor, comprising: forming a gate insulating layer on a semiconductor substrate, forming a thin amorphous silicon layer on the gate insulating layer, and heat treating in a gas atmosphere having nitrogen, and forming a gate Forming a polysilicon layer and doping impurities thereto. 제1항에 있어서, 상기 열처리는 NH3분위기에서 열처리기법으로 수초 내지 수십분동안 700℃내지 1000℃범위에서 행하여 비정질실리콘층은 질소로 도핑된 층이 되게 하는 것을 특징으로 하는 MOS 트랜지스터의 제조방법.The method of claim 1, wherein the heat treatment is performed in a range of 700 ° C. to 1000 ° C. for several seconds to several tens of minutes by a heat treatment method in an NH 3 atmosphere, so that the amorphous silicon layer becomes a layer doped with nitrogen. 제1항에 있어서, 폴리실리콘층에 도핑되는 불순물은 p+이며 폴리실리콘층 밑의 질소가 도핑된 비정질 실리콘층에 의해 게이트 절연층으로 상기 불순물의 확산이 방지되는 것을 특징으로 하는 MOS 트랜지스터의 제조방법.The MOS transistor of claim 1, wherein an impurity doped in the polysilicon layer is p + and diffusion of the impurity into the gate insulating layer is prevented by an amorphous silicon layer doped with nitrogen under the polysilicon layer. Way. 제3항에 있어서, 상기 불순물은 보론인 것을 특징으로 하는 MOS 트랜지스터 반도체의 제조방법.4. The method of claim 3 wherein the impurity is boron. 제1항에 있어서, 상기 박막의 질소를 함유하는 비정질 실리콘층은 500A 이하로 형성되는 것을 특징으로 하는 MOS트랜지스터 반도체 장치.The MOS transistor semiconductor device according to claim 1, wherein an amorphous silicon layer containing nitrogen of the thin film is formed at 500 A or less. MOS트랜지스터의 제조방법에 있어서, 반도체 기판상에 게이트 절연층을 형성하는 단계와, 상기 게이트 절연층상에 박막의 비정질 실리콘층을 형성하고, 질소 이온을 비정질 실리콘층에 주입하는 단계와, 게이트를 형성하기 위한 폴리실리콘층을 형성하고 불순물을 도핑시키는 단계를 포함하는 것을 특징으로 하는 MOS트랜지스터의 제조방법.A method of manufacturing a MOS transistor, comprising: forming a gate insulating layer on a semiconductor substrate, forming a thin amorphous silicon layer on the gate insulating layer, implanting nitrogen ions into the amorphous silicon layer, and forming a gate Forming a polysilicon layer for doping and doping the impurity comprising the step of manufacturing a MOS transistor. 제6항에 있어서, 상기 이온주입단계는 50keV의 낮은 에너지에서 1×1014내지 1×1016atoms/㎠도우즈 농도로 이온주입하는 것을 특징으로 하는 MOS트랜지스터의 제조방법.The method of claim 6, wherein the ion implantation step comprises ion implantation at a concentration of 1 × 10 14 to 1 × 10 16 atoms / cm 2 dose at a low energy of 50 keV. 제6항에 있어서, 폴리실리콘층에 도핑되는 불순물은 p+이며 폴리실리콘층 밑의 질소가 도핑된 비정질 실리콘층에 의해 게이트 절연층으로 상기 불순물의 확산이 방지되는 것을 특징으로 하는 MOS트랜지스터의 제조방법.The MOS transistor of claim 6, wherein the impurity doped into the polysilicon layer is p + and the diffusion of the impurity into the gate insulating layer is prevented by an amorphous silicon layer doped with nitrogen under the polysilicon layer. Way. 제8항에 있어서, 상기 불순물로 보론인 것을 특징으로 하는 MOS트랜지스터 반도체의 제조방법.The method of manufacturing a MOS transistor semiconductor according to claim 8, wherein the impurity is boron. 제6항에 있어서, 상기 박막의 질소를 함유하는 비정질실리콘층 500A 이하로 형성되는 것을 특징으로 하는 MOS트랜지스터 반도체 장치.7. The MOS transistor semiconductor device according to claim 6, wherein the silicon thin film is formed with an amorphous silicon layer of 500 A or less. 반도체 기판상에 형성된 게이트절연층과, 게이트 절연층위에 패턴 형성된 불순물원소를 포함하는 게이트전극과, 게이트 절연층 및 상기 게이트전극간에 형성된 박막의 질소를 함유하는 비정질실리콘층과, 게이트를 중심으로 기판영역내에 형성된 드레인, 소오스영역으로 구성되는 것을 특징으로 하는 MOS트랜지스터 반도체 장치.A gate insulating layer formed on the semiconductor substrate, a gate electrode including a patterned impurity element on the gate insulating layer, an amorphous silicon layer containing nitrogen of the gate insulating layer and the thin film formed between the gate electrode, and a substrate, mainly on the gate A MOS transistor semiconductor device comprising a drain and a source region formed in a region. 제9항에 있어서, 상기 박막의 질소를 함유하는 비정질실리콘층은 500A 이하로 형성되는 것을 특징으로 하는 MOS트랜지스터 반도체 장치.10. The MOS transistor semiconductor device according to claim 9, wherein an amorphous silicon layer containing nitrogen of the thin film is formed at 500 A or less. 제11항에 있어서, 게이트 절연층위에 패턴 형성된 불순물원소를 포함하는 게이트전극은 p+게이트로서 보론이 함유된 것을 특징으로 하는 MOS트랜지스터 반도체 장치.The MOS transistor semiconductor device of claim 11, wherein the gate electrode including an impurity element patterned on the gate insulating layer contains boron as a p + gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940002183A 1994-02-07 1994-02-07 Mos transistor device & method for fabricating the same KR0137901B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940002183A KR0137901B1 (en) 1994-02-07 1994-02-07 Mos transistor device & method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940002183A KR0137901B1 (en) 1994-02-07 1994-02-07 Mos transistor device & method for fabricating the same

Publications (2)

Publication Number Publication Date
KR950026029A true KR950026029A (en) 1995-09-18
KR0137901B1 KR0137901B1 (en) 1998-04-27

Family

ID=19376885

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940002183A KR0137901B1 (en) 1994-02-07 1994-02-07 Mos transistor device & method for fabricating the same

Country Status (1)

Country Link
KR (1) KR0137901B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100504188B1 (en) * 1997-12-30 2005-10-19 매그나칩 반도체 유한회사 Method for manufacturing gate electrode of semiconductor device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020002899A (en) * 2000-06-30 2002-01-10 박종섭 Method for forming gate electrode of semiconductor device
KR100713902B1 (en) * 2001-06-28 2007-05-07 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR100897248B1 (en) * 2002-12-26 2009-05-14 주식회사 하이닉스반도체 Method for forming gate-electrode in semiconductor device
KR100677042B1 (en) * 2004-12-23 2007-01-31 동부일렉트로닉스 주식회사 A method for forming gate of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100504188B1 (en) * 1997-12-30 2005-10-19 매그나칩 반도체 유한회사 Method for manufacturing gate electrode of semiconductor device

Also Published As

Publication number Publication date
KR0137901B1 (en) 1998-04-27

Similar Documents

Publication Publication Date Title
KR950007162A (en) Insulated gate semiconductor device and manufacturing method thereof
KR20000068441A (en) Asymmetrical transist0r with lightly and heavily doped drain regions and ultra-heavily doped source region
KR930011273A (en) Method of forming a semiconductor shallow junction and method of manufacturing a field effect transistor having a shallow source and drain region
US6426278B1 (en) Projection gas immersion laser dopant process (PGILD) fabrication of diffusion halos
KR930010982B1 (en) Manufacturing method of semiconductor device
KR980005412A (en) Ultra Low Junction Formation Method for Semiconductor Devices
KR930014767A (en) Semiconductor device and manufacturing method thereof
KR950026029A (en) MOS transistor semiconductor device and manufacturing method thereof
KR950010061A (en) Semiconductor device and manufacturing method thereof and bipolar transistor
KR100187387B1 (en) Activation method of ohmic layer of thin film transistor
JPH05267333A (en) Manufacture of mos type field effect transistor
KR970003447A (en) Annealing method of source / drain regions of MOS transistors
KR970054398A (en) Most transistor manufacturing method
KR940016961A (en) MOS transistor and its manufacturing method
KR970018259A (en) Transistor manufacturing method of semiconductor device
KR950010129A (en) Semiconductor device with MOS transistor and manufacturing method thereof
KR970003682A (en) MOS transistor manufacturing method with low doped drain structure
KR920013769A (en) LDD structure transistor manufacturing method
KR970013426A (en) Method of manufacturing thin film transistor
KR970072206A (en) Method of manufacturing transistor of semiconductor device
KR0156174B1 (en) Manufacture of mosfet
JPH03270137A (en) Manufacture of semiconductor device
KR980006502A (en) Method of manufacturing semiconductor device
KR950009978A (en) Manufacturing method of morph transistor
KR940012669A (en) Transistor Manufacturing Method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120120

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20130122

Year of fee payment: 16

EXPY Expiration of term