KR950015658A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- KR950015658A KR950015658A KR1019930024239A KR930024239A KR950015658A KR 950015658 A KR950015658 A KR 950015658A KR 1019930024239 A KR1019930024239 A KR 1019930024239A KR 930024239 A KR930024239 A KR 930024239A KR 950015658 A KR950015658 A KR 950015658A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- drain
- source
- metal silicide
- insulating layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 239000004065 semiconductor Substances 0.000 title claims abstract 4
- 229910052751 metal Inorganic materials 0.000 claims abstract 9
- 239000002184 metal Substances 0.000 claims abstract 9
- 229910021332 silicide Inorganic materials 0.000 claims abstract 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract 9
- 239000000758 substrate Substances 0.000 claims abstract 8
- 238000000034 method Methods 0.000 claims abstract 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 3
- 229920005591 polysilicon Polymers 0.000 claims abstract 3
- 238000005530 etching Methods 0.000 claims abstract 2
- 125000006850 spacer group Chemical group 0.000 claims abstract 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 4
- 239000010936 titanium Substances 0.000 claims 4
- 229910052719 titanium Inorganic materials 0.000 claims 4
- 238000010438 heat treatment Methods 0.000 claims 2
- 229910021341 titanium silicide Inorganic materials 0.000 claims 2
- 239000012535 impurity Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
반도체소자 제조방법에 있어서, 게이트전극과 소오스, 드레인 상부에 동시에 금속실리사이드를 형성할때 소오스, 드레인 상부에 너무 두꺼운 금속실리사이드가 형성되는 것을 방지하기 위하여 기판 상부에 게이트산화막, 폴리실리콘, 금속실리사이드 및 산화막으로 적층된 폴리사이드 게이트패턴을 형성하는 공정과 노출된 기판에 LDD영역을 형성하고, 게이트패턴 측벽에 절연층스페이서를 형성한 다음, 소오스 및 드레인을 형성하는 공정과, 상기 소오스 및 드레인 상부면에 금속실리사이드를 형성하는 공정과 절연층을 도포하고, 소오스, 및 드레인 상부의 절연층은 식각하여 콘택홀을 형성하는 공정을 포함하는 기술이다.In the semiconductor device manufacturing method, when the metal silicide is formed on the gate electrode, the source and the drain at the same time, the gate oxide film, the polysilicon, the metal silicide and Forming an LDD region on the exposed substrate, forming an insulating layer spacer on the sidewall of the gate pattern, forming a source and a drain, and forming a source and drain top surface. A method of forming a metal silicide and applying an insulating layer, and etching the insulating layer on the source and the drain to form contact holes.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 3 도의 (a)~(e)는 본 발명의 제1 실시예에 의해 모스펫을 제조하는 단계를 도시한 단면도.3 (a) to 3 (e) are cross-sectional views showing steps of manufacturing a MOSFET according to a first embodiment of the present invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930024239A KR100244789B1 (en) | 1993-11-15 | 1993-11-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930024239A KR100244789B1 (en) | 1993-11-15 | 1993-11-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950015658A true KR950015658A (en) | 1995-06-17 |
| KR100244789B1 KR100244789B1 (en) | 2000-02-15 |
Family
ID=19368084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930024239A KR100244789B1 (en) | 1993-11-15 | 1993-11-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100244789B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100863687B1 (en) | 2007-05-17 | 2008-10-16 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method of semiconductor device |
-
1993
- 1993-11-15 KR KR1019930024239A patent/KR100244789B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100244789B1 (en) | 2000-02-15 |
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| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20121022 Year of fee payment: 14 |
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| EXPY | Expiration of term |