KR960026459A - Transistor Manufacturing Method - Google Patents

Transistor Manufacturing Method Download PDF

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Publication number
KR960026459A
KR960026459A KR1019940038147A KR19940038147A KR960026459A KR 960026459 A KR960026459 A KR 960026459A KR 1019940038147 A KR1019940038147 A KR 1019940038147A KR 19940038147 A KR19940038147 A KR 19940038147A KR 960026459 A KR960026459 A KR 960026459A
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KR
South Korea
Prior art keywords
device isolation
ion implantation
forming
gate electrode
isolation layer
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KR1019940038147A
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Korean (ko)
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KR0167611B1 (en
Inventor
권성우
성진모
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김주용
현대전자산업 주식회사
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Priority to KR1019940038147A priority Critical patent/KR0167611B1/en
Publication of KR960026459A publication Critical patent/KR960026459A/en
Application granted granted Critical
Publication of KR0167611B1 publication Critical patent/KR0167611B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 기판(11)에 웰(well)(12), 소자분리 마스크 패턴(13), 소자분리층(14)을 차례로 형성하는 제1단계 ; 적어도 상기 소자 분리층의 끝부분에 이온주입을 실시하는 제2단계 ; 게이트 절연층(16), 게이트 전극(17)을 형성하는 제3단계 ; 소스/드레인을 형성하는 제4단계를 포함하는 것을 특징으로 하여, 게이트 전극이 활성영역을 충분히 덮지 않더라도 안정된 트랜지스터 동작을 얻을 수 있어, 소자의 안정성 및 집적도를 향상시키는 특유의 효과가 있는 트랜지스터 제조방법에 관한 것이다.The first step of forming a well (12), a device isolation mask pattern 13, a device isolation layer 14 in the semiconductor substrate 11; Performing a second ion implantation on at least an end of the device isolation layer; A third step of forming the gate insulating layer 16 and the gate electrode 17; And a fourth step of forming a source / drain, whereby a stable transistor operation can be obtained even if the gate electrode does not cover the active region sufficiently, thereby improving the stability and integration of the device. It is about.

Description

트랜지스터 제조방법Transistor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명에 따른 트랜지스터 제조 공정 단면도.2A to 2C are cross-sectional views of a transistor manufacturing process according to the present invention.

Claims (7)

반도체 기판에 웰(well), 소자분리 마스크 패턴, 소자분리층을 차례로 형성하는 제1단계 ; 적어도 상기 소자 분리층의 끝부분에 이온주입을 실시하는 제2단계 ; 게이트 절연층, 게이트 전극을 형성하는 제3단계 ; 소스/드레인을 형성하는 제4단계를 포함하는 것을 특징으로 하는 트랜지스터 제조방법.A first step of sequentially forming a well, a device isolation mask pattern, and a device isolation layer on the semiconductor substrate; Performing a second ion implantation on at least an end of the device isolation layer; A third step of forming a gate insulating layer and a gate electrode; And a fourth step of forming a source / drain. 제1항에 있어서, 상기 제2단계는, 상기 소자분리 마스크 패턴을 이온주입 배리어로 사용하여 이온주입을 실시하는 것을 특징으로 하는 트랜지스터 제조방법.The method of claim 1, wherein in the second step, ion implantation is performed using the device isolation mask pattern as an ion implantation barrier. 제1항에 있어서, 상기 제2단계는, 상기 웰에 도핑된 불순물과 동일한 종류의 불순물을 이온주입하는 것을 특징으로 하는 트랜지스터 제조방법.The method of claim 1, wherein in the second step, ion implantation of impurities of the same type as impurities doped into the well is performed. 제1항 내지 제3항에 있어서, 상기 이온주입시의 에너지는, 30 내지 60KeV로 설정하는 것을 특징으로 하는 트랜지스터 제조방법.The transistor manufacturing method according to claim 1, wherein the energy at the time of ion implantation is set to 30 to 60 KeV. 제1항에 있어서, 상기 제3단계에서, 상기 게이트 전극은 적어도 일측이 상기 소자분리층과 일정거리를 두도록 형성되는 것을 특징으로 하는 트랜지스터 제조방법.The method of claim 1, wherein in the third step, the gate electrode is formed such that at least one side thereof has a predetermined distance from the device isolation layer. 제1항에 있어서, 상기 제3단계 수행후, 상기 게이트 전극 측면에 스페이서를 형성하는 제5단계를 더 포함하는 것을 징으로 하는 트랜지스터 제조방법.The method of claim 1, further comprising a fifth step of forming a spacer on a side of the gate electrode after performing the third step. 제1항 또는 제6항에 있어서, 상기 제4단계에서, 소스/드레인을 위한 이온주입은 상기 소자분리층과 게이트 전극 사이에 노출된 부위에도 동시에 실시하는 것을 특징으로 하는 트랜지스터 제조방법.7. The method of claim 1 or 6, wherein in the fourth step, ion implantation for the source / drain is performed simultaneously on a portion exposed between the device isolation layer and the gate electrode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038147A 1994-12-28 1994-12-28 Method for fabricating transistor KR0167611B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038147A KR0167611B1 (en) 1994-12-28 1994-12-28 Method for fabricating transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038147A KR0167611B1 (en) 1994-12-28 1994-12-28 Method for fabricating transistor

Publications (2)

Publication Number Publication Date
KR960026459A true KR960026459A (en) 1996-07-22
KR0167611B1 KR0167611B1 (en) 1999-02-01

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