KR19990065141A - Self-aligned contact hole formation method - Google Patents

Abstract

Disclosed is a method of forming a self-aligned contact hole of a semiconductor device capable of preventing bridge defects and improving process margins. To this end, the present invention provides a first step of forming a gate pattern on a semiconductor substrate, a second step of stacking a fourth insulating film to a predetermined thickness on the entire surface of the semiconductor substrate on which the gate pattern is formed, and an interlayer on the semiconductor substrate on which the fourth insulating film is formed. A third step of stacking a fifth insulating film to be used as an insulating film, a fourth step of forming a photoresist pattern for forming a self-aligned contact hole on the fifth insulating film, and a part of the lower fifth insulating film using the photoresist pattern Etching to form a self-aligned contact hole exposing the gate pattern and the gate pattern, a sixth step of performing an ion implantation process with a photoresist pattern, the photoresist pattern is removed and the gate And a seventh step of removing the fourth insulating film covering the upper portion of the pattern. It provides.

Description

Self-aligned contact hole formation method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a self aligned contact hole during a manufacturing process of a semiconductor device.

As the degree of integration of the semiconductor device increases, the area of the cell region decreases, and as a result, the contact hole also decreases, resulting in an increase in contact resistance. In addition, a misalignment may occur in the photolithography process at the time of forming the contact hole, and an undesirably short may occur in another conductive layer adjacent to the conductive layer filling the contact hole. Accordingly, by forming the contact holes to be self-aligned without the photolithography process, it is possible to prevent short circuits due to misalignment in the photolithography process and to expose the wider area of the semiconductor substrate. A method of forming self aligned contact holes has been proposed. Such a self-aligned contact hole forming method is widely applied to actual processes because it meets the high integration and high reliability of semiconductor devices.

Such a method of forming a self-aligned contact hole, ① can suppress the occurrence of misalignment to suppress short circuit defects between the conductive layers, ② simplify the process by reducing the number of photographic and etching processes several times, ③ Compared to small contact holes, a wider area can be used as a contact area, which is advantageous in terms of reducing contact resistance.

1 to 6 are cross-sectional views according to a process sequence to explain a method for forming a self-aligned contact hole of a semiconductor device according to the prior art.

Referring to FIG. 1, a gate pattern including a gate oxide film 53, a gate electrode 55, a gate mask layer 55, and a gate spacer 61 is formed on a semiconductor substrate 51 having device isolation.

Referring to FIG. 2, a fourth insulating film 63 used as an etching stopper layer is formed on the entire surface of the semiconductor substrate 51 on which the gate pattern is formed to have a predetermined thickness, and an interlayer insulating film (interlayer) is formed. A fifth insulating film 65 used as a dielectric is formed on the fourth insulating film 63 to a sufficient thickness. Subsequently, after the process of planarizing the surface of the fifth insulating layer 65 is performed, a photoresist is applied and the exposure and development processes are performed to expose the lower gate pattern and the gate pattern to etch the self-aligned contact holes. To form a photoresist pattern 67.

Referring to FIG. 3, a self-aligned contact hole 69 exposing a portion between the gate pattern and the gate pattern by etching a portion of the fifth insulating layer 65 formed of an oxide layer under the photoresist pattern 67 as an etch mask. To form. In this case, the fourth insulating layer 63 below the fifth insulating layer 65 serves as an etching stopper.

Referring to FIG. 4, the photoresist pattern 67 used to form the self-aligned contact hole 69 is removed through an ashing process. Subsequently, a washing process is performed to remove the remaining photoresist.

Referring to FIG. 5, the fourth insulating layer, which is the etch stop layer inside the self-aligned contact hole, is removed from the resultant from which the photoresist pattern 67 is removed, and an ion implantation process is performed using the fifth insulating layer as an ion implantation mask. do.

FIG. 6 is a cross-sectional view when a cleaning process is performed to remove a native oxide layer (not shown) grown on a surface of a semiconductor substrate 100 that is a bottom of a self-aligned contact hole in a semiconductor substrate subjected to ion implantation. . The cleaning process is generally performed using wet cleaning, and the cleaning process performed to remove the natural oxide film is an interlayer insulating film, ie, a fifth insulating film having an etch rate 10 times higher due to damage during ion implantation. 65 is over etched. In this case, overetching increases the size of the self-aligned contact hole. In the case of a semiconductor device having a fine design rule such as DRAM or more than one gigabyte, the adjacent conductive layers may be severe. May cause bridge defects. In addition, bridge defects between adjacent conductive layers result in at least a worsening of the process margins without causing them.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for forming a self-aligned contact hole capable of suppressing a problem of increasing the size of a self-aligned contact hole even after an ion implantation process is performed on the self-aligned contact hole.

1 to 6 are cross-sectional views illustrating cross-sectional views of a semiconductor substrate in a process sequence to explain a method for forming a self-aligned contact hole of a semiconductor device according to the prior art.

7 to 12 are cross-sectional views illustrating cross-sections of semiconductor substrates in a process sequence to explain a method for forming self-aligned contact holes in a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

100: semiconductor substrate, 102: first insulating film,

104: first conductive layer, 106: second insulating film,

108: third insulating film, 110: fourth insulating film,

112: fifth insulating film, 114: photoresist pattern,

116: self aligned contact hole, 118: ion beam.

According to an aspect of the present invention, a first step of forming a gate pattern on a semiconductor substrate, a second step of stacking a fourth insulating film to a predetermined thickness on the entire surface of the semiconductor substrate on which the gate pattern is formed, and the fifth step A third step of stacking a fifth insulating film to be used as an interlayer insulating film on a semiconductor substrate on which the insulating film is formed, a fourth step of forming a photoresist pattern for forming a self-aligned contact hole in the resultant, and using the photoresist pattern A fifth step of forming a self-aligned contact hole for etching a portion of the lower fifth insulating layer to expose the gate pattern and the gate pattern, and a sixth step of performing an ion implantation process with the photoresist pattern present; A seventh step of removing the photoresist pattern and removing a fourth insulating layer covering an upper portion of the gate pattern; It provides a method for forming a self-aligned contact hole, characterized in that.

According to a preferred embodiment of the present invention, the method of forming the gate pattern of the first step includes a first insulating film which is a gate oxide film formed on a semiconductor substrate, a first conductive layer on the first insulating film, and a first conductive layer on the first conductive layer. It is preferable to form a gate pattern made of a second insulating film, and a third insulating film which is a gate spacer formed on both sides of the first insulating film, the first conductive layer, and the second insulating film, wherein the second insulating film is formed of a nitride film or a nitride film and an oxide film. It is preferable to use a composite film of which the third insulating film is a low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD) nitride film (SiN), the third insulating film is formed to a thickness of 500 ~ 1000∼ Is suitable.

Preferably, the fourth insulating film is a nitride film formed by low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD), and preferably has a thickness in a range of 50 to 250 GPa. HDP: A film formed using an oxide film formed of high density plasma (BPSG), an oxide film formed of BPSG (Boro Phosphorus Silicate Glass), and SACVD (sub-atmosphere CVD) method. It is preferable.

Further, according to a preferred embodiment of the present invention, after stacking the fifth insulating film of the third step, it is suitable to further planarize the third insulating film, and the self-aligned contact hole of the fifth step In order to etch a portion of the fifth insulating film to form a metal, it is preferable to proceed with the fourth insulating film remaining on the surface of the gate pattern using dry etching.

In addition, it is preferable to further proceed with the cleaning process after the ion implantation process of the sixth step, and the method of removing the fourth insulating film of the seventh step is preferably using dry etching, and the fourth insulating film of the seventh step It is preferable to perform a washing | cleaning process further after removing.

According to the present invention, when the self-aligned contact hole is formed during the manufacturing process of a semiconductor device, the contact hole size caused by the overetching of the interlayer insulating film in the wet cleaning process following the ion implantation process is caused. Bridge defects and process margins can be solved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 7, a gate oxide film made of a first insulating film 102, a gate electrode made of a first conductive layer 104, and a semiconductor substrate 100 on which a trench or LOCOS device isolation film is formed, and The second insulating film 106 is sequentially formed by using a nitride film (SiN) using a low pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD) or a composite film of a nitride film and an oxide film. The first insulating film 102, the first conductive layer 104, and the second insulating film 106 are sequentially stacked to form a pattern by laminating and patterning. Subsequently, a third insulating film 108, for example, a nitride film formed by LPCVD or PECVD, is stacked to a thickness of 500 to 1000 GPa and anisotropic etching is performed on the resultant to form the first insulating film 102 and the first conductive layer 104. ) And the second insulating film 106 are formed on both side walls of which the first insulating film 106 is sequentially stacked, thereby forming the first insulating film 102, the first conductive layer 104, the second insulating film 106, and the third insulating film 106. A gate pattern composed of the insulating film 108 is formed.

Referring to FIG. 8, a fourth insulating film 110 serving as an etching stopper in a subsequent process is formed on the semiconductor substrate 100 on which the gate pattern is formed, such as a nitride film (SiN) formed by LPCVD or PECVD. The semiconductor substrate 100 having the gate pattern formed thereon is deposited to a thickness of ˜250 μs. Subsequently, a fifth insulating film 112 as an interlayer dielectric, for example, an oxide film formed of HDP (High Density Plasma), an oxide film formed by Boro Phosphorus Silicate Glass (BPSG), and a sub-atmosphere CVD (SACVD) method. The selected one of the layers is stacked to a thickness of 3000 to 6000 GPa, and a planarization process such as etchback or chemical mechanical polishing (CMP) is performed to eliminate the step of the fifth insulating layer 112. The sub-atmosphere CVD (SACVD) refers to a chemical vapor deposition method in which a pressure of a chamber is advanced between an atmospheric pressure and a low pressure in a chemical vapor deposition (CVD) process. Subsequently, a photoresist is coated on the fifth insulating layer 112, and a photoresist for forming a self aligned contact hole is performed by performing an exposure and development process. The pattern 114 is formed. As for the thickness of such photoresist pattern 114, about 5000-7000 micrometers is suitable.

Referring to FIG. 9, the photoresist pattern 114 is etched to etch a portion of the lower fifth insulating layer 112 by performing a selective dry etch using a difference in etching ratio between the nitride layer and the oxide layer. A self aligned contact hole 116 is formed to expose the gate pattern and the gate pattern. In this case, the fourth insulating layer 110 serves as an etching stopper in the dry etching process.

Referring to FIG. 10, in the case of a DRAM device, a capacitor for storing data of a semiconductor memory device is formed through the self-aligned contact hole 116. That is, the region in which the self-aligned contact holes are formed corresponds to the source region of the transistor. At this time, in order to improve contact resistance between the capacitor and the source region, an ion implantation process of scanning the ion beam 118 on the entire surface of the semiconductor substrate is performed. In this case, the fourth insulating layer 110 covers the gate pattern in the self-aligned contact hole. Since the photoresist pattern 114 covers the upper portion of the fifth insulating layer 112, the damage of the fifth insulating layer 112 that may occur in the ion implantation process in which the ion beam 118 is scanned is effectively suppressed. can do.

Referring to FIG. 11, a photoresist pattern is removed from an ion implanted semiconductor substrate through an ashing process, and a cleaning process for removing residual polymer, for example, a first wet cleaning process (1). Proceed with 'st wet cleaning process'.

Referring to FIG. 12, in the result of the first wet cleaning process, the fourth insulating layer 110 covering the portion of the gate pattern and the semiconductor substrate 100, for example, a nitride film by LPCVD or PECVD may be selectively selected using dry etching. To remove it. The reason why the dry etching is used instead of the wet etching is to minimize the damage that may occur at the side ends of the semiconductor substrate 100 and the gate pattern. In this case, when the fourth insulating layer 110 on the semiconductor substrate 100 is removed, a native oxide layer (not shown) grows on the surface of the semiconductor substrate 100, and a material filling a self-aligned contact hole. For example, a second oxide wet cleaning process may be performed before removing the natural oxide layer in a step before being buried in polysilicon. In this case, since the fifth insulating film 112, which is an interlayer insulating film, is damaged in the ion implantation process and the etching rate is increased by 10 times or more, the fifth insulating film including self-aligned contact holes is formed in the second cleaning process. Overetching occurs at 112 to increase the size of the self-aligned contact holes, causing bridge defects or lowering process margins. However, in the present invention, since the ion implantation was performed while the photoresist pattern was covered on the fifth insulating film 112 in the ion implantation process, the damage to the fifth insulating film 112, which is an interlayer insulating film, was almost reduced in the ion implantation process. Does not occur. Therefore, the etching rate of the fifth insulating layer 112 is increased in the second wet cleaning process, so that the fifth insulating layer 112 having the self-aligned contact holes is overetched, thereby preventing the problem of increasing the size of the contact hole. In this case, it is possible to prevent a problem in which bridge defects or process margins fall.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

Therefore, according to the present invention described above, when forming the self-aligned contact hole in the manufacturing process of the semiconductor device, the contact hole size by the over-etching of the interlayer insulating film in the wet cleaning process following the ion implantation process Bridge defects and process margins caused by the increase can be solved.

Claims (15)

Forming a gate pattern on the semiconductor substrate; A second step of stacking a fourth insulating film to a predetermined thickness on an entire surface of the semiconductor substrate on which the gate pattern is formed; Stacking a fifth insulating film to be used as an interlayer insulating film on a semiconductor substrate on which the fifth insulating film is formed; Forming a photoresist pattern for forming a self-aligned contact hole on the resultant; A fifth step of etching a portion of the lower fifth insulating layer using the photoresist pattern to form a self-aligned contact hole exposing the gate pattern and the gate pattern; A sixth step of performing an ion implantation process with the photoresist pattern present; And And removing the photoresist pattern and removing the fourth insulating layer covering the upper portion of the gate pattern. The method of claim 1, The method of forming the gate pattern of the first step includes a first insulating film, which is a gate oxide film formed on a semiconductor substrate, a first conductive layer on the first insulating film, a second insulating film on the first conductive layer, and the first insulating film. And forming a gate pattern including a first insulating layer and a third insulating layer, which is a gate spacer formed on both sides of the second insulating layer. The method of claim 2, And the second insulating layer is formed using a nitride film formed by low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD) or a composite film of a nitride film and an oxide film. The method of claim 2, The third insulating film is formed using a nitride film formed by low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD). The method of claim 2, And the third insulating film has a thickness in the range of 500 to 1000 GPa. The method of claim 1, The fourth insulating layer is formed using a nitride film formed by low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD). The method of claim 1, And the fourth insulating film is formed in a thickness range of 50 to 250 kPa. The method of claim 1, And the fifth insulating layer is formed using one selected from an oxide film formed of high density plasma (HDP), an oxide film formed by BPSG, and a sub-atmosphere CVD (SACVD) method. The method of claim 1, And the fifth insulating film is finally formed in a thickness range of 3000 to 6000 microns. The method of claim 1, And stacking the third insulating film after stacking the fifth insulating film in the third step, further comprising planarizing the third insulating film. The method of claim 1, And etching the portion of the fifth insulating film to form the self-aligned contact hole of the fifth step using dry etching. The method of claim 1, And etching a portion of the fifth insulating film to form the self-aligned contact hole of the fifth step, so that the fourth insulating film on the exposed gate pattern surface remains. The method of claim 1, further comprising, after the sixth step of the ion implantation process, performing a wet cleaning process. The method of claim 1, The method of removing the fourth insulating film of the seventh step is using a dry etching method of forming a self-aligned contact. The method of claim 1, And performing a wet cleaning process for removing the native oxide film after removing the fourth insulating film of the seventh step.