KR20040110792A - The method for forming shall trench isolation in semiconductor device - Google Patents
The method for forming shall trench isolation in semiconductor device Download PDFInfo
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Abstract
Description
본 발명은 반도체 소자의 얕은 트랜치 소자분리막 형성방법에 관한 것으로, 특히, 리버스 에치백 공정을 이용하여 균일한 두께의 얕은 소자분리막을 형성하는 반도체 소자의 얕은 트랜치 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a shallow trench isolation layer of a semiconductor device, and more particularly, to a method of forming a shallow trench isolation layer of a semiconductor device using a reverse etch back process to form a shallow isolation layer having a uniform thickness.
일반적으로, 반도체 메모리와 같은 반도체 소자를 제조할 시 다수의 소자들이 집적되는 활성영역을 전기적으로 서로 절연시키기 위해 소자분리 기술이 사용되고 있다. 최근 반도체 소자의 집적도가 증가하면서 전기적으로 절연성이 우수하며 또한 버즈빅(bird's beak)과 같은 현상으로부터 자유로우면서도 소자분리를 위한 필드영역의 면적을 감소시킬 수 있는 얕은 트랜치 소자분리막(Shallow Trench Isolation: 이하, STI라 함.)이 개발되어 널리 이용되고 있다. 일반적으로, 0.18㎛ 이하의 STI 공정에서는 갭필용 산화막으로 고밀도 플라즈마(High Density Plasma: 이하, HDP라 함.) 산화막이 사용되고 있다. 상기 HDP 산화막은 좁은 트랜치에 채워지는 경우 갭필 능력이 우수하며 후속 세정공정에서 실각률이 낮아 산화막 손실을 줄일 수 있는 장점이 있다.In general, when fabricating a semiconductor device, such as a semiconductor memory, device isolation technology is used to electrically insulate an active region in which a plurality of devices are integrated. With the recent increase in the degree of integration of semiconductor devices, a shallow trench isolation (Shallow Trench Isolation) which is excellent in electrical insulation and free from phenomena such as bird's beak and can reduce the area of the field region for device isolation. , STI, has been developed and widely used. In general, a high density plasma (High Density Plasma :, HDP) oxide film is used as the gap fill oxide film in an STI process of 0.18 µm or less. When the HDP oxide film is filled in a narrow trench, the gap fill ability is excellent and the loss rate of the oxide film is reduced due to a low loss rate in the subsequent cleaning process.
도 1a 내지 도 1c는 종래 기술에 의한 반도체 소자의 얕은 트랜치 소자분리막 형성방법을 설명하기 위한 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a shallow trench isolation layer of a semiconductor device according to the related art.
도 1a를 참조하면, 반도체 기판(100)상에 질화막과, 포토레지스트막(미도시)을 순차적으로 형성한다. 이어, 상기 포토레지스트막(미도시)을 패터닝하여 필드영역을 정의한 후 패터닝된 포토레지스트막(미도시)을 마스크로 하고 플라즈마를 이용하여 상기 질화막을 건식식각함으로써 질화막 패턴(102)을 형성한다.Referring to FIG. 1A, a nitride film and a photoresist film (not shown) are sequentially formed on the semiconductor substrate 100. Subsequently, the photoresist layer (not shown) is patterned to define a field region, and the nitride layer pattern 102 is formed by dry etching the nitride layer using a patterned photoresist layer (not shown) as a mask.
그 다음, 질화막 패턴(102)을 마스크로 하고 플라즈마를 이용하여 반도체 기판(100)을 건식식각함으로써 트랜치(104)를 형성한다.Next, the trench 104 is formed by dry etching the semiconductor substrate 100 using the nitride film pattern 102 as a mask.
그 다음, 상기 결과물 전면에 갭필용 산화막으로서 고밀도 플라즈마 화학기상증착(High Density Plasma Chemical Vapor Deposition)에 의한 HDP 산화막(106)을 증착하여 트랜치(104)가 HDP 산화막(106)으로 충분히 채워질 수 있도록 한다.Next, the HDP oxide 106 is deposited by high density plasma chemical vapor deposition as a gap fill oxide on the entire surface of the resultant, so that the trench 104 can be sufficiently filled with the HDP oxide 106. .
도 1b를 참조하면, HDP 산화막(106)의 증착공정이 완료된 후 리버스 에치백 마스크(미도시)를 사용하여 질화막 패턴의 밀도가 높은 영역에 대해서 리버스(reverse) 에치백 공정을 진행한다. 여기서, 리버스 에치백 공정을 진행하는 것은 질화막 패턴의 밀도가 높은 활성영역의 낮추어 질화막 패턴의 밀도가 낮은 영역과의 단차를 줄임으로써 후속되는 화학기계적연마(Chemical Mechanical Polishing: 이하, CMP라 함.) 공정을 진행할 시 디싱(dishing)의 발생을 방지하기 위함이다.Referring to FIG. 1B, after the deposition process of the HDP oxide layer 106 is completed, a reverse etch back process is performed on a region having a high density of the nitride film pattern using a reverse etch back mask (not shown). Here, the reverse etchback process is performed by lowering the active region having a high density of the nitride film pattern and reducing the step difference with the low density region of the nitride pattern (Chemical Mechanical Polishing: hereinafter referred to as CMP). This is to prevent the occurrence of dishing during the process.
상기 리버스 에치백 공정을 진행함에 따라 질화막 패턴의 밀도가 높은 활성영역에 있어 그 활성영역 상부에 증착된 HDP 산화막(106)이 제거된다. 도 1b에서 참조부호 106a는 리버스 에치백 후의 HDP 산화막(106)을 나타낸다.As the reverse etchback process is performed, the HDP oxide layer 106 deposited on the active region in the high density of the nitride layer pattern is removed. In Fig. 1B, reference numeral 106a denotes the HDP oxide film 106 after reverse etch back.
도 1c를 참조하면, 화학기계적연마(Chemical Mechanical Polishing: 이하, CMP라 함.) 공정에 의해 상기 리버스 에치된 HDP 산화막(106)을 화학기계적으로 연마한다. 이러한 CMP 공정은 질화막 패턴(102)이 노출될 때까지 진행된다. 도 1c에서 참조부호 102a는 CMP 후의 질화막 패턴을, 106b는 CMP 후의 HDP 산화막을 나타낸다.Referring to FIG. 1C, the reverse etched HDP oxide film 106 is chemically mechanically polished by a chemical mechanical polishing (hereinafter, referred to as CMP) process. This CMP process is performed until the nitride film pattern 102 is exposed. In Fig. 1C, reference numeral 102a denotes a nitride film pattern after CMP, and 106b denotes an HDP oxide film after CMP.
상기 CMP 공정을 완료한 후 질화막 패턴(102)를 제거하여 STI를 형성한다.After the CMP process is completed, the nitride film pattern 102 is removed to form an STI.
그러나, 상술한 바와 같은 종래의 기술에서는 HDP 산화막의 평탄화를 위해 CMP 공정전에 리버스 에치백을 실시함에도 불구하고 CMP 공정 후에 질화막 패턴의 편차와 STI의 디싱 문제가 여전히 발생한다.However, in the conventional technology as described above, despite the reverse etch back before the CMP process for the planarization of the HDP oxide film, the nitride film pattern deviation and the STI dishing problem still occur after the CMP process.
따라서, 본 발명의 목적은 상기 문제점을 해결하기 위해 CMP 공정 전후에 가각각 리버스 에치백 공정을 실시함에 의해 균일한 두께의 얕은 소자분리막을 구현할 수 있는 반도체 소자의 얕은 트랜치 소자분리막 형성방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a shallow trench isolation layer formation method of a semiconductor device capable of implementing a shallow isolation layer of uniform thickness by performing a reverse etch back process before and after the CMP process to solve the above problems. There is.
도 1a 내지 도 1c는 종래 기술에 의한 반도체 소자의 얕은 트랜치 소자분리막 형성방법을 설명하기 위한 공정단면도.1A to 1C are cross-sectional views illustrating a method of forming a shallow trench isolation layer in a semiconductor device according to the prior art;
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 얕은 트랜치 소자분리막 형성방법을 설명하기 위한 공정단면도.2A to 2D are cross-sectional views illustrating a method of forming a shallow trench isolation layer in a semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호설명* Code descriptions for the main parts of the drawings
200: 반도체 기판 202: 질화막 패턴200: semiconductor substrate 202: nitride film pattern
204: 트랜치 206: HDP 산화막204: trench 206: HDP oxide film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 얕은 트랜치 소자분리막 형성방법은, 반도체 기판상의 미리 정의된 활성영역에 질화막 패턴을 형성하는 단계; 상기 질화막 패턴을 마스크로 하여 트랜치를 형성하는 단계; 상기 결과물의 상부에 갭필용 산화막을 증착하여 상기 트랜치를 갭필링하는 단계; 상기 질화막 패턴의 밀도가 높은 영역을 제 1리버스 에치백하는 하는 단계; 상기 질화막 패턴의 밀도가 높은 영역과 상기 질화막 패턴의 밀도가 낮은 영역간의 단차를 줄이기 위해 상기 증착된 갭필용 산화막을 화학기계적으로 연마하는 단계; 상기 질화막 패턴의 밀도가 높은 영역을 제 2리버스 에치백하는 단계; 및 상기 질화막 패턴을 식각하여 제거하는 단계를 구비하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming a shallow trench isolation layer of a semiconductor device, the method including: forming a nitride film pattern on a predefined active region on a semiconductor substrate; Forming a trench using the nitride film pattern as a mask; Gapfilling the trench by depositing an oxide film for gapfill on top of the resultant material; Etching back a region having a high density of the nitride film pattern; Chemically polishing the deposited gap fill oxide film in order to reduce a step difference between a high density of the nitride film pattern and a low density of the nitride film pattern; Etching back a second reverse region of the nitride film pattern having a high density; And etching to remove the nitride film pattern.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 얕은 트랜치 소자분리막 형성방법을 설명하기 위한 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of forming a shallow trench isolation layer in a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 얕은 트랜치 소자분리막 형성방법을 도 2a 내지 도 2d를 참조하여 설명하면 다음과 같다.A method of forming a shallow trench isolation layer of a semiconductor device according to the present invention will be described with reference to FIGS. 2A through 2D.
도 2a를 참조하면, 반도체 기판(200)상에 질화막과, 포토레지스트막(미도시)을 순차적으로 형성한다. 이어, 상기 포토레지스트막(미도시)을 패터닝하여 필드영역을 정의한 후 패터닝된 포토레지스트막(미도시)을 마스크로 하고 플라즈마를 이용하여 상기 질화막을 건식식각함으로써 질화막 패턴(202)을 형성한다.Referring to FIG. 2A, a nitride film and a photoresist film (not shown) are sequentially formed on the semiconductor substrate 200. Subsequently, the photoresist layer (not shown) is patterned to define a field region, and the nitride layer pattern 202 is formed by dry etching the nitride layer using a patterned photoresist layer (not shown) as a mask.
그 다음, 질화막 패턴(202)을 마스크로 하고 플라즈마를 이용하여 반도체 기판(200)을 건식식각함으로써 트랜치(204)를 형성한다.Next, the trench 204 is formed by dry etching the semiconductor substrate 200 using the nitride film pattern 202 as a mask.
그 다음, 상기 결과물 전면에 갭필용 산화막으로서 고밀도 플라즈마 화학기상증착(High Density Plasma Chemical Vapor Deposition)에 의한 HDP 산화막(206)을 증착하여 트랜치(204)가 HDP 산화막(206)으로 충분히 채워질 수 있도록 한다.Next, an HDP oxide film 206 by high density plasma chemical vapor deposition is deposited on the entire surface of the resultant, so that the trench 204 can be sufficiently filled with the HDP oxide film 206. .
도 2b를 참조하면, HDP 산화막(106)의 증착공정이 완료된 후 리버스 에치백 마스크(미도시)를 사용하여 질화막 패턴의 밀도가 높은 영역에 대해서 첫 번째 리버스(reverse) 에치백 공정을 진행한다. 이 때, HDP 산화막(206a)은 반도체 기판(200)의 활성영역 있어 가장자리 표면에 2000~3000Å 정도의 두께로 잔존하게 된다.Referring to FIG. 2B, after the deposition process of the HDP oxide layer 106 is completed, a first reverse etch back process is performed on a region having a high density of the nitride film pattern using a reverse etch back mask (not shown). At this time, the HDP oxide film 206a remains in the active area of the semiconductor substrate 200 at a thickness of about 2000 to 3000 Å on the edge surface.
도 2c를 참조하면, CMP 공정에 의해 상기 리버스 에치된 갭필용 산화막(206a)을 화학기계적으로 연마함으로써, 질화막 패턴(202)의 밀도가 높은 영역과 질화막 패턴(202)의 밀도가 낮은 영역간의 단차를 줄인다. 이 때, HDP 산화막(206c)은 질화막 패턴(202)의 밀도가 높은 영역에 있어 반도체 기판(200)의활성영역 표면에 약 500Å정도의 두께로 잔존하게 되고, 질화막 패턴(202)의 밀도가 낮은 영역의 고밀도 플라즈마 산화막은 완전히 연마되어 해당 질화막 패턴이 노출된다.Referring to FIG. 2C, the gap between the region of high density of the nitride film pattern 202 and the region of low density of the nitride film pattern 202 is chemically polished by the reverse etched gap fill oxide film 206a by a CMP process. Reduce At this time, the HDP oxide film 206c remains on the surface of the active region of the semiconductor substrate 200 in the region of high density of the nitride film pattern 202 with a thickness of about 500 GPa, and the density of the nitride film pattern 202 is low. The high density plasma oxide film in the region is completely polished to expose the nitride film pattern.
도 2d를 참조하면, 상기 CMP 공정을 완료한 후 질화막 패턴(202)의 밀도가 높은 영역에 대해서 두 번째 리버스 에치백 공정을 실시한다. 이 때, 상기 질화막 패턴(202) 상부의 모든 HDP 산화막을 제거하여 질화막 패턴(202)을 노출시킨다. 도 2d에서 참조부호 206d는 두 번째 리버스 에치백 공정 후의 HDP 산화막을 나타낸다.Referring to FIG. 2D, after completing the CMP process, a second reverse etch back process is performed on the high density region of the nitride film pattern 202. In this case, all of the HDP oxide layers on the nitride layer pattern 202 are removed to expose the nitride layer pattern 202. Reference numeral 206d in FIG. 2D denotes the HDP oxide film after the second reverse etch back process.
본 발명에 따라 리버스 에치백 공정은 질화막 패턴와 HDP 산화막의 선택비가 높은 상태에서 실시되는 것이 바람직하며, 두 번째 리버스 에치백 공정의 경우 선택비가 50:1 이상으로 높은 상태에서 리버스 에치백 공정이 진행된다.According to the present invention, the reverse etchback process is preferably performed in a state where the selectivity of the nitride pattern and the HDP oxide layer is high, and in the case of the second reverse etchback process, the reverse etchback process is performed while the selectivity is higher than 50: 1. .
상기 두 번째 에치백 공정을 완료한 후 질화막 패턴(202)를 제거하여 STI를 형성한다.After completing the second etch back process, the nitride layer pattern 202 is removed to form an STI.
이상에서와 같이, 본 발명은 CMP 공정 전후에 각각 리버스 에치백 공정을 실시함으로써, 질화막 패턴의 두께 편차를 제거함과 아울러 CMP의 선택비로 인한 디싱을 방지할 수 있고, 이로 인해 균일한 두께의 얕은 소자분리막을 구현할 수 있다.As described above, according to the present invention, by performing the reverse etch back process before and after the CMP process, the thickness variation of the nitride film pattern can be eliminated, and dishing due to the selection ratio of CMP can be prevented. Separation membrane can be implemented.
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US8796107B2 (en) | 2011-11-28 | 2014-08-05 | Samsung Electronics Co., Ltd. | Methods for fabricating semiconductor devices |
CN109461696A (en) * | 2018-10-15 | 2019-03-12 | 上海华虹宏力半导体制造有限公司 | A kind of production method of fleet plough groove isolation structure |
CN112750755A (en) * | 2019-10-30 | 2021-05-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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US8796107B2 (en) | 2011-11-28 | 2014-08-05 | Samsung Electronics Co., Ltd. | Methods for fabricating semiconductor devices |
CN109461696A (en) * | 2018-10-15 | 2019-03-12 | 上海华虹宏力半导体制造有限公司 | A kind of production method of fleet plough groove isolation structure |
CN112750755A (en) * | 2019-10-30 | 2021-05-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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