KR20050003013A - Fabricating method forming isolation layer in semiconductor device - Google Patents
Fabricating method forming isolation layer in semiconductor device Download PDFInfo
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- KR20050003013A KR20050003013A KR1020030043139A KR20030043139A KR20050003013A KR 20050003013 A KR20050003013 A KR 20050003013A KR 1020030043139 A KR1020030043139 A KR 1020030043139A KR 20030043139 A KR20030043139 A KR 20030043139A KR 20050003013 A KR20050003013 A KR 20050003013A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Abstract
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로 특히, 셀(cell) 영역에서의 트렌치 매립을 용이하게 함과 동시에 페리(peri) 영역에서 PMOS 소자의 특성열화를 방지한 반도체 소자의 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to forming a device isolation film of a semiconductor device, which facilitates trench filling in a cell region and prevents deterioration of characteristics of a PMOS device in a peri region. It is about a method.
반도체 소자를 제조하는 경우, 소자를 전기적으로 분리시키기 위하여 소자분리막을 형성한다. 이러한 소자분리막을 형성하는 방법으로는 통상적으로 열산화막을 이용한 국부적 산화방법(Local Oxidation of Silicon : LOCOS)과 집적도에 유리한 트렌치(trench) 구조를 이용한 얕은 트렌치 소자분리막 형성방법(Shallow Trench Isolation : STI)이 많이 적용되고 있다.When fabricating a semiconductor device, an element isolation film is formed to electrically isolate the device. As a method of forming such a device isolation layer, a local trench method using a thermal oxide film (Local Oxidation of Silicon: LOCOS) and a shallow trench isolation method (STI) using a trench structure which is advantageous for integration are used. This is applied a lot.
그 중에서 열산화막 등을 이용한 로코스(LOCOS) 기법은, 반도체 소자의 디자인 룰(design rule)의 감소에 따른 필드 산화막의 열화와 같은 공정의 불안정 요인과, 버즈비크(bird's beak)에 따른 활성영역의 감소와 같은 문제점을 갖고 있기 때문에 이를 해결할 수 있는 소자분리 기술에 요구되었다.Among them, the LOCOS technique using a thermal oxide film has a process instability such as deterioration of a field oxide film due to a decrease in design rules of a semiconductor device, and an active region according to a bird's beak. Because of the problems such as the reduction of the required device isolation technology that can solve this problem.
이에 따라 대두된 기술이 얕은 트렌치 소자분리 기법(Shallow Trench Isolation : 이하, STI)이다. STI 기법은 반도체 기판에 트렌치를 형성하고, 트렌치 내부를 절연막으로 매립(gap-fill)함으로써 활성영역과 필드영역을 정의하는 소자분리 기법으로, 이러한 STI 기법은 초고집적 반도체 소자 제조 공정에의 적용이유망한 기술이다.The emerging technology is the shallow trench isolation (STI). The STI technique is a device isolation technique that defines an active region and a field region by forming a trench in a semiconductor substrate and gap-filling the inside of the trench with an insulating film. The STI technique is not applicable to an ultra-high density semiconductor device manufacturing process. It is a promising technology.
이러한 STI 공정에서 트렌치의 측벽과 바닥의 실리콘 기판을 보호하기 위하여 라이너 질화막(liner nitride)을 사용하는 방법이 널리 사용되고 있는데, 라이너 질화막에 의하여 실리콘 기판에 응집된 스트레스가 감소하고, 소자 분리막에서 실리콘 기판으로의 도판트(dopant)들의 확산작용이 억제되는 등의 효과를 얻을 수 있어, 결국 소자의 리프레쉬 특성이 향상되는 것으로 알려져 있다.In this STI process, a method using a liner nitride film is widely used to protect the silicon substrate on the sidewalls and the bottom of the trench. The stress deposited on the silicon substrate by the liner nitride film is reduced, and the silicon substrate in the device isolation layer is reduced. It is known that the effect of diffusion of dopants into the substrate is suppressed, and thus the refresh characteristics of the device are improved.
이러한 장점을 가지는 라이너 질화막을 이용한 STI 형성방법을 도1a 내지 도1c를 참조하여 설명한다.An STI forming method using a liner nitride film having such an advantage will be described with reference to FIGS. 1A to 1C.
먼저, 도1a에 도시된 바와같이 반도체 기판(10) 상에 패드산화막(11)과 패드질화막(12) 및 감광막(13)을 차례로 형성한 다음, 노광/현상공정을 진행하여 소자분리막이 형성될 영역의 패드산화막(11)과 패드질화막(12)을 완전히 제거하는 패터닝 작업을 실시하여 반도체 기판(10)을 노출시킨다.First, as shown in FIG. 1A, a pad oxide film 11, a pad nitride film 12, and a photoresist film 13 are sequentially formed on a semiconductor substrate 10, and then an exposure / development process is performed to form a device isolation film. The semiconductor substrate 10 is exposed by patterning to completely remove the pad oxide film 11 and the pad nitride film 12 in the region.
다음으로 감광막(13)을 제거하고 패드질화막(12)을 식각마스크로 하여 반도체 기판(10)을 일정두께 식각하여 소자분리막이 매립될 트렌치 구조를 형성한다.Next, the photoresist layer 13 is removed and the semiconductor layer 10 is etched by a predetermined thickness using the pad nitride layer 12 as an etching mask to form a trench structure in which the device isolation layer is embedded.
다음으로 도1b에 도시된 바와같이 트렌치 측벽과 바닥의 실리콘 기판을 보호하기 위한 목적으로 일정두께의 실리콘 기판을 열산화법을 이용하여 산화시키고(측벽산화막 형성), 이어서 측벽산화막(15) 상에 다시 일정두께의 얇은 라이너 질화막(16)을 화학기상증착(Chemical Vapor Deposition)법을 이용해 증착한다. 다음으로 라이너 질화막(16) 상에 다시 얇은 두께의 라이너 산화막(미도시)을 CVD 법으로 증착하면, 트렌치용 라이너가 형성된다.Next, as shown in FIG. 1B, a silicon substrate having a predetermined thickness is oxidized using a thermal oxidation method (side wall oxide film formation) for the purpose of protecting the silicon sidewalls of the trench sidewalls and the bottom, and then on the sidewall oxide film 15 again. A thin liner nitride film 16 having a predetermined thickness is deposited by using chemical vapor deposition (Chemical Vapor Deposition) method. Next, when a thin liner oxide film (not shown) is deposited on the liner nitride film 16 by CVD, a liner for trenches is formed.
다음으로 소자분리막으로 사용될 절연막(17)으로 트렌치를 매립한후, 평탄화를 위한 화학기계연마를 수행한다.Next, after the trench is filled with the insulating film 17 to be used as the device isolation film, chemical mechanical polishing for planarization is performed.
다음으로 도1c에 도시된 바와같이, 패드 질화막(12)을 제거시킬 목적으로 인산용액(H3PO4)을 이용한 세정공정을 진행하고, 잔류한 패드산화막(11)을 제거할 목적으로 HF 또는 BOE 용액을 이용한 세정공정을 진행하면, 도1c에 도시된 바와같은 트렌지 소자분리막이 완성된다.Next, as illustrated in FIG. 1C, a cleaning process using a phosphate solution (H 3 PO 4 ) is performed for the purpose of removing the pad nitride film 12, and HF or the purpose of removing the remaining pad oxide film 11 is performed. When the cleaning process using the BOE solution is performed, a trench isolation layer as shown in FIG. 1C is completed.
그러나 디자인 룰이 계속 감소하면서 셀 영역에 형성된 트렌치에 대한 매립이 어려워지는 문제가 발생하였다. 이를 해결하기 위해 트렌치 측벽에 형성되는 측벽산화막의 두께를 계속 감소시키는 것이 현재의 추세이다.However, as design rules continue to decrease, it is difficult to bury trenches formed in the cell region. In order to solve this problem, it is a current trend to continuously reduce the thickness of the sidewall oxide film formed on the trench sidewalls.
하지만, 이와같이 측벽산화막의 두께가 감소하면서 PMOS 소자특성이 열화되는 또 다른 문제가 발생하게 되었는데, 그 원인으로는 측벽산화막과 라이너 질화막 사이의 계면에 트랩 차지(trap charge)가 형성되어 양이온을 트렌치 측벽에 파일 업(file up) 시키며, 결국, PMOS 소자에서의 누설전류 특성을 악화시키는 것으로 알려져 있다.However, as the thickness of the sidewall oxide film is reduced, another problem arises in that the PMOS device characteristics are deteriorated. As a cause, a trap charge is formed at the interface between the sidewall oxide film and the liner nitride film, and thus positive ions are formed in the trench sidewalls. It is known to file up and ultimately deteriorate the leakage current characteristic of the PMOS device.
결국, 라이너 질화막을 사용하는 STI 구조에서는 트렌치 매립을 양호하게 하려면 측벽산화막의 두께를 감소시켜야만 하지만, PMOS 소자 특성이 열화를 방지하려면 측벽산화막의 두께를 증가시켜야 하는 문제가 대두되었고, 현재까지 이 문제를 해결하기 위하여 많은 실험이 진행되고 있는 것으로 알려져 있다.As a result, in the STI structure using the liner nitride film, it is necessary to reduce the thickness of the sidewall oxide film in order to improve the trench filling, but the problem of increasing the thickness of the sidewall oxide film to prevent the degradation of the PMOS device characteristics has been raised. Many experiments are known to solve the problem.
본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 셀 영역에서의 트렌치 매립의 용이하게 함과 동시에 페리영역에서 PMOS 소자 특성의 열화를 방지한 반도체 소자의 소자분리막 형성방법을 제공함을 그 목적으로 한다.Disclosure of Invention The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device which facilitates trench filling in a cell region and prevents deterioration of PMOS device characteristics in a ferry region. do.
도1a 내지 도1c는 종래의 소자분리막 형성방법을 도시한 공정단면도,1A through 1C are cross-sectional views illustrating a conventional method of forming an isolation layer;
도2a 내지 도2d는 본 발명의 일실시예에 따른 소자분리막 형성방법을 도시한 공정 단면도.2A through 2D are cross-sectional views illustrating a method of forming an isolation layer in accordance with an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
20 : 기판20: substrate
21 : 패드산화막21: pad oxide film
22 : 패드질화막22: pad nitride film
23 : 패드감광막23: pad photosensitive film
24 : 트렌치24: trench
25 : 제 1 측벽산화막25: first sidewall oxide film
26 : 감광막26: photosensitive film
27 : 제 2 측벽산화막27: second sidewall oxide film
28 : 제 3 측벽산화막28: third sidewall oxide film
상기한 목적을 달성하기 위한 본 발명은, 셀 영역과 페리영역을 갖는 반도체 소자에 있어서, 셀 영역과 페리영역을 포함하는 기판 상에 소자분리를 위한 트렌치를 형성하는 단계; 상기 트렌치의 측벽에 제 1 측벽산화막을 형성하는 단계; 페리 영역만을 덮는 마스크를 형성하고, 상기 셀 영역에 형성된 상기 제 1 측벽산화막을 제거하는 단계; 상기 마스크를 제거한 후, 열산화법을 이용하여 상기 페리영역에는 두께가 두꺼운 제 2 측벽산화막을 형성하고, 상기 셀 영역에는 두께가 상대적으로 얇은 제 3 측벽산화막을 형성하는 단계; 및 상기 제 2 및 제 3 측벽산화막 상에 라이너 질화막 및 라이너 산화막을 형성하는 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a semiconductor device having a cell region and a ferry region, the method comprising: forming a trench for device isolation on a substrate including the cell region and the ferry region; Forming a first sidewall oxide film on the sidewalls of the trench; Forming a mask covering only the ferry region, and removing the first sidewall oxide film formed in the cell region; After the mask is removed, a second sidewall oxide film having a thick thickness is formed in the ferry region by a thermal oxidation method, and a third sidewall oxide film having a relatively thin thickness is formed in the cell region; And forming a liner nitride film and a liner oxide film on the second and third sidewall oxide films.
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 종래의 라이너 질화막을 사용하는 STI 방법에서 발생하는 셀 영역의 트렌치 매립불량 문제와 페리영역의 PMOS 소자특성의 열화문제를 동시에 해결한 발명이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention solves a problem of poor trench filling in a cell region and a problem of deterioration of PMOS device characteristics in a ferry region, which occur in a conventional STI method using a liner nitride film.
이를 위한 본 발명에서는 셀 영역에는 얇은 두께의 측벽산화막을 형성하고 페리영역에서는 두꺼운 두께의 측벽산화막을 형성하여 셀 영역의 트렌치 매립불량문제와 페리영역의 PMOS 소자특성의 열화문제를 동시에 해결하였다.In the present invention, a thin sidewall oxide film is formed in the cell region and a thick sidewall oxide film is formed in the ferry region to solve the problem of poor trench filling in the cell region and degradation of PMOS device characteristics of the ferry region.
즉, PMOS 소자가 형성되지 않으면서 좁은 트렌치를 갖는 셀 영역에서는 트렌치 매립에 유리하도록 측벽산화막의 두께를 감소시키고, 넓은 트렌치가 형성되어 트렌치 매립이 용이한 페리영역에서는 PMOS 특성을 향상시키도록 측벽산화막의 두께를 증가시켰다.That is, the thickness of the sidewall oxide film is reduced in the cell region having a narrow trench without forming a PMOS device, and the sidewall oxide film is improved to improve the PMOS characteristics in the ferry region in which a wide trench is formed to facilitate the trench filling. Increased thickness.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.
도2a 내지 도2d는 본 발명의 일실시에에 따른 트렌치 소자분리막 형성공정을 셀영역과 페리영역을 포함하여 도시한 공정단면도로서 이를 참조하며 설명한다.2A to 2D illustrate a process of forming a trench isolation layer in accordance with an embodiment of the present invention with reference to a process cross-sectional view including a cell region and a ferry region.
먼저, 도2a에 도시된 바와같이 반도체 기판(20) 상에 패드산화막(21)과 패드질화막(22) 및 감광막(23)을 차례로 형성한 다음, 노광/현상공정을 진행하여 소자분리막이 형성될 영역의 패드산화막(21)과 패드질화막(22)을 완전히 제거하는 패터닝 작업을 실시하여 반도체 기판(20)을 노출시킨다.First, as shown in FIG. 2A, the pad oxide layer 21, the pad nitride layer 22, and the photoresist layer 23 are sequentially formed on the semiconductor substrate 20, and then an exposure / development process is performed to form an isolation layer. The semiconductor substrate 20 is exposed by patterning to completely remove the pad oxide film 21 and the pad nitride film 22 in the region.
다음으로 감광막(미도시)을 제거하고 패드질화막(22)을 식각마스크로 하여 반도체 기판(20)을 일정두께 식각하여 소자분리막이 매립될 트렌치 구조를 형성한다.Next, the photoresist layer (not shown) is removed and the semiconductor substrate 20 is etched by a predetermined thickness using the pad nitride layer 22 as an etching mask to form a trench structure in which the device isolation layer is embedded.
다음으로 도2b에 도시된 바와같이 트렌치 측벽과 바닥의 실리콘 기판을 보호하기 위한 목적으로 일정두께의 실리콘 기판을 열산화법을 이용하여 산화시켜 제 1측벽산화막(25)을 형성한다. 이때, 제 1 측벽산화막(25)은 셀 영역과 페리 영역 모두에 형성되며, 30 ∼ 100Å의 두께를 갖는 것이 바람직하다.Next, as shown in FIG. 2B, the silicon substrate having a predetermined thickness is oxidized by thermal oxidation for the purpose of protecting the silicon substrates on the trench sidewalls and the bottom to form the first sidewall oxide film 25. At this time, the first sidewall oxide film 25 is formed in both the cell region and the ferry region, and preferably has a thickness of 30 to 100 GPa.
이어서, 셀 영역과 페리 영역을 포함하는 전체 구조상에 감광막(26)을 형성한 후, 셀 영역에 형성된 감광막만을 제거하는 패터닝 공정을 수행한다. 결과적으로 도 2b에 도시된 바와같이 페리 영역에만 감광막(26)이 형성되어 있고, 셀 영역은 노출되어 있다.Subsequently, after the photoresist layer 26 is formed on the entire structure including the cell region and the ferry region, a patterning process of removing only the photoresist layer formed in the cell region is performed. As a result, as shown in FIG. 2B, the photosensitive film 26 is formed only in the ferry region, and the cell region is exposed.
이어서, HF 용액 또는 완충산화식각제(Buffered Oxide Etchant : BOE)을 이용하여 셀 영역에 형성된 제 1 측벽산화막(25)만을 제거한다. 이때 페리영역에는 감광막이 형성되어 있으므로, 페리영역에 형성된 제 1 측벽산화막(25)은 제거되지 않는다.Subsequently, only the first sidewall oxide layer 25 formed in the cell region is removed by using an HF solution or a buffered oxide etchant (BOE). At this time, since the photosensitive film is formed in the ferry region, the first sidewall oxide film 25 formed in the ferry region is not removed.
다음으로 PR strip 공정을 진행하여 페리영역을 덮고 있는 감광막(26)을 모두 제거한다. 이어서, 열산화공정을 도입하여 트렌치 내부에 30 ∼ 100Å의 두께를 갖는 열산화막을 형성한다.Next, the PR strip process is performed to remove all of the photoresist layer 26 covering the ferry region. Subsequently, a thermal oxidation process is introduced to form a thermal oxide film having a thickness of 30 to 100 Pa in the trench.
결과적으로 도2d에 도시된 바와같이 페리영역에서는 제 1 측벽산화막(25) 상에 30 ∼ 100Å의 두께를 갖는 측벽산화막이 다시 형성되므로, 두께가 두꺼운 측벽산화막이 형성되며, 셀 영역에서는 트렌치 측벽의 실리콘 기판 상에 직접 측벽산화막이 형성되므로, 페리영역에 형성된 측벽산화막 보다는 얇은 두께를 갖는다.As a result, as shown in FIG. 2D, in the ferry region, a sidewall oxide film having a thickness of 30 to 100 측벽 is formed again on the first sidewall oxide film 25, so that a thick sidewall oxide film is formed, and in the cell region, the trench sidewall oxide film is formed. Since the sidewall oxide film is formed directly on the silicon substrate, the sidewall oxide film is thinner than the sidewall oxide film formed in the ferry region.
설명의 편의를 위해 페리영역에 형성된 두께가 상대적으로 두꺼운 측벽산화막을 제 2 측벽산화막(27)이라고 하며, 셀 영역에 형성된 두께가 상대적으로 얇은 측벽산화막을 제 3 측벽산화막(28)이라고 하기로 한다.For convenience of description, the relatively thick sidewall oxide film formed in the ferry region is referred to as the second sidewall oxide film 27, and the relatively thin sidewall oxide film formed in the cell region is referred to as the third sidewall oxide film 28. .
이때, 제 2 측벽산화막의 두께는 100 ∼ 200Å 의 두께를 갖는 것이 바람직하며, 제 3 측벽산화막의 두께는 30 ∼ 100Å 의 두께를 갖는 것이 바람직하다.At this time, the thickness of the second sidewall oxide film preferably has a thickness of 100 to 200 kPa, and the thickness of the third sidewall oxide film preferably has a thickness of 30 to 100 kPa.
이와같은 공정을 통해 셀 영역에 형성된 제 3 측벽산화막(28)은 두께가 얇기 때문에 후속 트렌치 매립공정이 용이하게 진행될 수 있으며, 페리영역에 형성된 제 2 측벽산화막(27)은 두께가 두껍기 때문에 제 2 측벽산화막(27)과 라이너 질화막(후속공정으로 형성됨) 사이의 계면함정에 의한 PMOS 소자의 특성저하를 방지할 수 있다.Since the third sidewall oxide layer 28 formed in the cell region is thin in this process, the subsequent trench filling process may be easily performed, and the second sidewall oxide layer 27 formed in the ferry region may have a large thickness. It is possible to prevent the deterioration of the characteristics of the PMOS device due to the interface trap between the sidewall oxide film 27 and the liner nitride film (formed by a subsequent process).
이와같이 제 2 및 제 3 측벽산화막(27, 28)을 형성한 이후에, 제 2 측벽산화막(27) 및 제 3 측벽산화막(28) 상에 일정두께의 얇은 라이너 질화막(미도시)을 증착한다. 다음으로 라이너 질화막 상에 다시 얇은 두께의 라이너 산화막을 CVD 법으로 증착하면, 트렌치용 라이너가 형성된다.After forming the second and third sidewall oxide films 27 and 28 in this manner, a thin liner nitride film (not shown) having a predetermined thickness is deposited on the second sidewall oxide film 27 and the third sidewall oxide film 28. Next, a thin liner oxide film is further deposited on the liner nitride film by CVD to form a trench liner.
다음으로 소자분리막을 완성하기 위한 일련의 공정이 수행되어 STI 구조를 완성한다.Next, a series of processes to complete the device isolation layer is performed to complete the STI structure.
즉, 소자분리막으로 사용될 절연막으로 트렌치를 매립한후, 평탄화를 위한 화학기계연마를 수행한다. 이어서 패드 질화막을 제거시킬 목적으로 인산용액(H3PO4)을 이용한 세정공정을 진행하고, 잔류한 패드산화막을 제거할 목적으로 HF 또는 BOE 용액을 이용한 세정공정을 진행하면, 트렌지 소자분리막이 완성된다.That is, after filling the trench with an insulating film to be used as the device isolation film, chemical mechanical polishing for planarization is performed. Subsequently, a cleaning process using a phosphate solution (H 3 PO 4 ) is performed to remove the pad nitride film, and a cleaning process using a HF or BOE solution is performed to remove the remaining pad oxide film. Is completed.
본 발명에서는 셀 영역에는 두께가 매우 얇은 측벽산화막을 형성하였기 때문에 HDP 산화막 등을 이용한 트렌치 매립에 매우 유리하며 또한, 페리 영역에 형성된 측벽산화막은 그 두께가 매우 두껍기 때문에 측벽산화막과 라이너 질화막 계면의 계면함정에 의해 유발되는 PMOS 소자 특성의 열화를 방지할 수 있다.In the present invention, since the sidewall oxide film having a very thin thickness is formed in the cell region, it is very advantageous for the trench filling using an HDP oxide film or the like, and since the sidewall oxide film formed in the ferry region is very thick, the interface between the sidewall oxide film and the liner nitride film interface is formed. Deterioration of the PMOS device characteristics caused by the trap can be prevented.
이상에서 설명한 바와 같이 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.
본 발명을 반도체 소자의 제조에 적용하면, 셀 영역에서의 트렌치 매립을 용이하게 함과 동시에 페리 영역에서 PMOS 소자 특성의 열화를 방지할 수 있다.When the present invention is applied to the manufacture of semiconductor devices, it is possible to facilitate trench filling in the cell region and to prevent deterioration of PMOS device characteristics in the ferry region.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100868654B1 (en) * | 2006-12-27 | 2008-11-12 | 동부일렉트로닉스 주식회사 | Method of forming trench in a semiconductor device |
| US8786047B2 (en) | 2012-03-26 | 2014-07-22 | SK Hynix Inc. | Semiconductor device with isolation layer, electronic device having the same, and method for fabricating the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100868654B1 (en) * | 2006-12-27 | 2008-11-12 | 동부일렉트로닉스 주식회사 | Method of forming trench in a semiconductor device |
| US8786047B2 (en) | 2012-03-26 | 2014-07-22 | SK Hynix Inc. | Semiconductor device with isolation layer, electronic device having the same, and method for fabricating the same |
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