KR20040058798A - Method for forming device isolation film of semiconductor device - Google Patents
Method for forming device isolation film of semiconductor device Download PDFInfo
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- KR20040058798A KR20040058798A KR1020020085189A KR20020085189A KR20040058798A KR 20040058798 A KR20040058798 A KR 20040058798A KR 1020020085189 A KR1020020085189 A KR 1020020085189A KR 20020085189 A KR20020085189 A KR 20020085189A KR 20040058798 A KR20040058798 A KR 20040058798A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
Abstract
Description
본 발명은 반도체 소자의 소자 분리막 형성 방법에 관한 것으로, 특히 STI(Shallow Trench Isolation) 구조의 소자 분리막을 HDP(High Density Plasma) 산화막을 이용하여 형성하는 경우 HDP 산화막을 형성하고 이를 포토레지스트 패턴을 이용하여 리세스함으로써 트렌치의 면비(Aspect Ratio)를 감소시켜 종래의 갭-필링 산화막을 이용하면서도 보이드(void)를 방지하고 갭-필링 특성을 향상시킨 반도체 소자의 소자 분리막 형성 방법에 관한 것이다.The present invention relates to a method for forming a device isolation layer of a semiconductor device, and in particular, when the device isolation layer having a shallow trench isolation (STI) structure is formed using an HDP (High Density Plasma) oxide layer, an HDP oxide layer is formed and the photoresist pattern is used. The present invention relates to a method of forming a device isolation layer of a semiconductor device in which the aspect ratio of a trench is reduced by recessing, thereby preventing voids and improving gap-filling characteristics while using a conventional gap-filling oxide film.
반도체 소자가 고집적화됨에 따라 소자 분리 영역 및 활성 영역을 정의하는 소자 분리막의 형성 방법 중의 하나로 STI 구조가 제안되었다. 이러한 STI 구조의소자 분리막을 형성하는 물질로서 HDP CVD 산화막이 사용되는데, 이러한 종래 기술에 따른 반도체 소자의 소자 분리막 형성 방법은 도 1a 내지 도 1d를 참조하여 설명하면 다음과 같다.As semiconductor devices have been highly integrated, an STI structure has been proposed as one of a method of forming a device isolation layer defining device isolation regions and active regions. An HDP CVD oxide film is used as a material for forming the device isolation film having the STI structure. The method of forming the device isolation film of the semiconductor device according to the related art is described below with reference to FIGS. 1A to 1D.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 소자 분리막 형성 방법을 도시한 단면도들이다. 도 1a 내지 도 1d를 참조하면, 반도체 기판(10) 상부에 버퍼 산화막(20) 및 질화막(30)을 순차적으로 형성한 후 질화막(30)과 버퍼 산화막(20) 및 반도체 기판(10)을 식각하여 트렌치(50)를 형성한다. 그 다음에, 트렌치(50)의 표면을 산화시켜 산화막(40)을 형성한 후 트렌치(50)를 매립하는 절연막(60)을 상기 구조물의 전면에 형성하고 절연막(60)을 평탄화 식각하여 질화막(30)을 노출시킨 후 질화막(30) 및 버퍼 산화막(20)을 제거하여 소자 분리막(70)을 형성한다.1A to 1D are cross-sectional views illustrating a method of forming a device isolation layer of a semiconductor device according to the prior art. 1A through 1D, after the buffer oxide film 20 and the nitride film 30 are sequentially formed on the semiconductor substrate 10, the nitride film 30, the buffer oxide film 20, and the semiconductor substrate 10 are etched. To form the trench 50. Next, after oxidizing the surface of the trench 50 to form an oxide film 40, an insulating film 60 filling the trench 50 is formed on the entire surface of the structure, and the insulating film 60 is flattened and etched to form a nitride film ( After exposing 30, the nitride layer 30 and the buffer oxide layer 20 are removed to form the device isolation layer 70.
HDP CVD 산화막은 통상적으로 면비가 약 4.5 이하인 트렌치를 형성하는 경우에만 사용할 수 있으며, 상기 종래 기술에 따른 반도체 소자의 소자 분리막 형성 방법은 HDP 산화막의 갭-필링 특성의 한계로 인하여 면비가 5 이상인 트렌치의 경우 내부에 보이드가 발생하고 이로 인하여 누설 전류가 발생하여 소자의 특성이 저하된다는 문제점이 있으며, 따라서, 면비가 5 이상인 85㎚ 이하의 소자에는 사용할 수 없다.The HDP CVD oxide film can be generally used only when forming a trench having a surface ratio of about 4.5 or less, and the method of forming a device isolation layer of a semiconductor device according to the prior art is a trench having a surface ratio of 5 or more due to the limitation of gap-filling characteristics of the HDP oxide film In this case, voids are generated therein, and therefore, leakage currents are generated, thereby degrading the characteristics of the device. Therefore, they cannot be used in devices of 85 nm or less having a surface ratio of 5 or more.
상기 문제점을 해결하기 위하여 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법은 제1 HDP 산화막을 형성하고 이를 포토레지스트 패턴을 이용하여 리세스함으로써 트렌치의 면비(Aspect Ratio)를 감소시키고 제2 산화막을 트렌치 내에 형성하여 소자 분리막을 형성함으로써, 면비가 5 이상인 경우에도 종래의 HDP 산화막을 이용하여 보이드가 없으며, 소자 분리 특성이 우수하고 85㎚이하의 소자에서도 사용할 수 있는 반도체 소자의 소자 분리막을 형성하는 것을 그 목적으로 한다.In order to solve the above problem, the method of forming a device isolation layer of a semiconductor device according to the present invention forms a first HDP oxide layer and recesses it using a photoresist pattern, thereby reducing the aspect ratio of the trench and trenching the second oxide layer. Forming a device isolation film to form a device isolation film to form a device isolation film of a semiconductor device having no voids using a conventional HDP oxide film even when the aspect ratio is 5 or more, and having excellent device isolation characteristics and can be used in devices of 85 nm or less. For that purpose.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 소자 분리막 형성 방법을 도시한 단면도들.1A to 1D are cross-sectional views illustrating a method of forming a device isolation layer of a semiconductor device according to the prior art.
도 2a 내지 도 2h는 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법을 도시한 단면도들.2A to 2H are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 소자 분리막 형성 방법은 반도체 기판 상부에 패드 산화막 및 패드 질화막을 순차적으로 형성하는 단계와, 상기 패드 질화막, 패드 산화막 및 반도체 기판을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치 내부의 반도체 기판 표면을 산화시켜 열산화막을 형성하는 단계와, 상기 트렌치를 포함하는 상기 구조물 전면에 배리어 질화막과 상기 트렌치를 소정 깊이 매립하는 제1 산화막을 순차적으로 형성하는 단계와, 상기 트렌치 내부에 상기 트렌치를 소정 깊이 매립하는 포토레지스트 패턴을 형성하는 단계와, 상기 제1 HDP 산화막 및 포토레지스트 패턴을 전면 식각하여 상기 트렌치 하부의 제1 산화막을 노출시키는 단계와, 상기 트렌치를 매립하는 제2 산화막을 상기 구조물 전면에 형성하는 단계와, 상기 제2 산화막을 식각하여 상기 배리어 질화막을 노출시키는 단계 및 상기 배리어 질화막, 패드 질화막 및 패드 산화막을 제거하는 단계를 포함하는 것을 특징으로 한다.A method of forming a device isolation layer of a semiconductor device according to the present invention may include sequentially forming a pad oxide layer and a pad nitride layer on an upper surface of a semiconductor substrate, forming a trench by etching the pad nitride layer, the pad oxide layer, and the semiconductor substrate, and forming the trench. Oxidizing a surface of a semiconductor substrate to form a thermal oxide film, sequentially forming a barrier nitride film and a first oxide film buried a predetermined depth in front of the structure including the trench; Forming a photoresist pattern filling the trench a predetermined depth, etching the entire first HDP oxide film and the photoresist pattern to expose the first oxide film under the trench, and forming a second oxide film filling the trench Forming a surface of the structure, and forming the second oxide film. Each will be characterized by including the steps of removing the barrier nitride film, the pad nitride and pad oxide layer to expose the nitride film barrier.
이하에서는, 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법을 첨부된 도면을 참조하여 상세하게 설명한다.Hereinafter, a method of forming an isolation layer of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법을도시한 단면도들이다. 도 2a 내지 도 2h를 참조하면, 반도체 기판(100) 상부에 패드 산화막(110) 및 패드 질화막(120)을 순차적으로 형성한다. 여기서, 패드 산화막(110)의 두께는 30 내지 150Å인 것이 바람직하며, 패드 질화막(120)의 두께는 200 내지 1200Å인 것이 바람직하다.2A to 2H are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to the present invention. 2A to 2H, a pad oxide film 110 and a pad nitride film 120 are sequentially formed on the semiconductor substrate 100. Here, the thickness of the pad oxide film 110 is preferably 30 to 150 kPa, and the thickness of the pad nitride film 120 is 200 to 1200 kPa.
다음에는, 패드 질화막(120), 패드 산화막(110) 및 반도체 기판(100)을 식각하여 트렌치(130)를 형성한다. 여기서 트렌치(130)는 반도체 기판(100)을 2000 내지 3000Å 정도 식각하여 형성하는 것이 바람직하다.Next, the trench 130 is formed by etching the pad nitride layer 120, the pad oxide layer 110, and the semiconductor substrate 100. The trench 130 may be formed by etching the semiconductor substrate 100 at about 2000 to 3000 microseconds.
그 다음에, 트렌치(130) 내부의 반도체 기판(100) 표면을 산화시켜 열산화막(140)을 형성한다. 여기서, 반도체 기판 표면의 산화 공정에 의하여 트렌치의 코너 부분이 라운딩되어 후속 공정에서 형성되는 갭-필링 산화막과 반도체 기판 사이의 인터페이스 전하 트랩 형성을 억제할 수 있다.Next, the surface of the semiconductor substrate 100 inside the trench 130 is oxidized to form a thermal oxide film 140. Here, the corner portion of the trench may be rounded by an oxidation process of the surface of the semiconductor substrate to suppress the formation of an interface charge trap between the gap-filling oxide film and the semiconductor substrate formed in a subsequent process.
다음에는, 트렌치(130)를 포함하는 상기 구조물 전면에 배리어 질화막(150)과 트렌치(130)를 소정 깊이 매립하는 제1 산화막(160)을 순차적으로 형성한다. 여기서, 배리어 질화막(150)은 CVD 방법을 이용하여 50 내지 200Å의 두께로 형성하는 것이 바람직하며, 제1 산화막(160)은 트렌치(130) 하부에서의 두께가 200 내지 1000Å인 HDP 산화막인 것이 바람직하다.Next, a first oxide film 160 is formed on the entire surface of the structure including the trench 130 to fill the barrier nitride film 150 and the trench 130 with a predetermined depth. Here, the barrier nitride film 150 may be formed to a thickness of 50 to 200 GPa using the CVD method, and the first oxide film 160 may be an HDP oxide film having a thickness of 200 to 1000 GPa under the trench 130. Do.
그 다음에, 트렌치(130) 내부에 트렌치(130)를 소정 깊이 매립하는 포토레지스트 패턴(170)을 형성한다. 구체적으로는, 트렌치(130)를 매립하는 포토레지스트막(미도시)을 상기 구조물의 전면에 형성한 후 전면 식각하여 형성한다. 여기서, 포토레지스트 패턴(170)의 두께는 200 내지 1000Å인 것이 바람직하다.Next, a photoresist pattern 170 is formed in the trench 130 to fill the trench 130 to a predetermined depth. Specifically, a photoresist film (not shown) filling the trench 130 is formed on the entire surface of the structure, and then formed by etching the entire surface. Here, it is preferable that the thickness of the photoresist pattern 170 is 200-1000 GPa.
다음에는, 제1 HDP 산화막(160) 및 포토레지스트 패턴(130)을 전면식각하여 트렌치(130) 하부의 제1 산화막(165)을 노출시킨다. 여기서, 배리어 질화막(150)이 식각 정지층으로 작용하며, 트렌치(130) 하부의 제1 산화막(165)은 산화막과 포토레지스트 간의 식각 속도 차이에 의하여 중심 부분이 오목하게 된다.Next, the first HDP oxide layer 160 and the photoresist pattern 130 are etched on the entire surface to expose the first oxide layer 165 under the trench 130. Here, the barrier nitride layer 150 serves as an etch stop layer, and the center portion of the first oxide layer 165 under the trench 130 is concave due to the difference in etching rate between the oxide layer and the photoresist.
그 다음에, 트렌치(130)를 매립하는 제2 산화막(180)을 바람직하게는 HDP 산화막을 이용하여 상기 구조물 전면에 형성하고 평탄화 식각하여 배리어 질화막(150)을 노출시킨 후 배리어 질화막(150), 패드 질화막(120) 및 패드 산화막(110)을 제거하여 소자 분리막(190)을 형성한다.Next, a second oxide film 180 filling the trench 130 is preferably formed on the entire surface of the structure by using an HDP oxide film and planarized to expose the barrier nitride film 150 to expose the barrier nitride film 150, The pad nitride layer 120 and the pad oxide layer 110 are removed to form the device isolation layer 190.
본 발명에 따른 반도체 소자의 소자 분리막 형성 방법은 제1 HDP 산화막을 형성하고 이를 포토레지스트 패턴을 이용하여 리세스함으로써 트렌치의 면비(Aspect Ratio)를 감소시키고 제2 산화막을 트렌치 내에 형성하여 소자 분리막을 형성함으로써, 면비가 5 이상인 경우에도 종래의 HDP 산화막을 이용하여 보이드가 없으며, 소자 분리 특성이 우수하고 85㎚이하의 소자에서도 사용할 수 있는 반도체 소자의 소자 분리막을 제공한다.In the method of forming a device isolation layer of a semiconductor device according to the present invention, a first HDP oxide layer is formed and recessed using a photoresist pattern, thereby reducing the aspect ratio of the trench and forming a second oxide layer in the trench to form the device isolation layer. The present invention provides a device isolation film of a semiconductor device in which there is no void using a conventional HDP oxide film even when the aspect ratio is 5 or more, and the device isolation characteristic is excellent and can be used in devices of 85 nm or less.
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---|---|---|---|---|
KR100556527B1 (en) * | 2004-11-04 | 2006-03-06 | 삼성전자주식회사 | Method of forming a tranch isolation layer and method of manufacturing a non-volatile memory device |
KR100613342B1 (en) * | 2004-12-16 | 2006-08-21 | 동부일렉트로닉스 주식회사 | Semiconductor device and method of manufacturing the same |
KR100694976B1 (en) * | 2004-12-20 | 2007-03-14 | 주식회사 하이닉스반도체 | Method of forming a field oxide layer in semiconductor device |
-
2002
- 2002-12-27 KR KR1020020085189A patent/KR100596876B1/en not_active IP Right Cessation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100556527B1 (en) * | 2004-11-04 | 2006-03-06 | 삼성전자주식회사 | Method of forming a tranch isolation layer and method of manufacturing a non-volatile memory device |
KR100613342B1 (en) * | 2004-12-16 | 2006-08-21 | 동부일렉트로닉스 주식회사 | Semiconductor device and method of manufacturing the same |
KR100694976B1 (en) * | 2004-12-20 | 2007-03-14 | 주식회사 하이닉스반도체 | Method of forming a field oxide layer in semiconductor device |
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