KR20010059029A - A method for forming a field oxide of a semiconductor device - Google Patents
A method for forming a field oxide of a semiconductor device Download PDFInfo
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- KR20010059029A KR20010059029A KR1019990066407A KR19990066407A KR20010059029A KR 20010059029 A KR20010059029 A KR 20010059029A KR 1019990066407 A KR1019990066407 A KR 1019990066407A KR 19990066407 A KR19990066407 A KR 19990066407A KR 20010059029 A KR20010059029 A KR 20010059029A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Abstract
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 특히 광폭의 소자분리영역에서 소자분리막이 얇게 형성되는 디싱 ( dishing ) 현상을 최소화시켜 평탄화된 소자분리막을 형성하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a technology for forming a planarized device isolation film by minimizing dishing phenomenon in which a device isolation film is thinly formed in a wide device isolation region.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디맨젼 ( dimension ) 을 축소하는 것과, 소자간에 존재하는 분리영역 ( isolation region ) 의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리기술이 메모리 셀 사이즈 ( memory cell size ) 를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of isolation regions existing between devices. Device isolation technology determines the memory cell size in terms of size.
소자분리절연막을 제조하는 종래기술로는 절연물 분리방식의 로코스 ( LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함 ) 방법, 실리콘기판상부에 산화막, 다결정실리콘층, 질화막순으로 적층한 구조의 피.비.엘. ( Poly - Buffed LOCOS, 이하에서 PBL 이라 함 ) 방법, 기판에 홈을 형성한 후에 절연물질로 매립하는 트렌치 ( trench ) 방법 등이 있다.Conventional techniques for manufacturing device isolation insulating films include LOCOS (LOCOS: LOCOS) method, an oxide film, a polysilicon layer, and a nitride film on a silicon substrate. B.L. (Poly-Buffed LOCOS, hereinafter referred to as PBL) method, a trench method of embedding an insulating material after forming a groove in the substrate, and the like.
그러나, 상기 LOCOS 방법은 소자의 고집적화에따라, 소자분리절연막 산화공정시 산소의 측면확산에 의한 버즈빅 ( bird's beak ) 현상에 의해 활성영역이 작아지는 문제점을 가지고 있으며, 또한 좁은 영역에서 산화막 성장이 잘되지 않는 현상 ( field oxide ungrown ) 또는 소자분리산화막의 씨닝 ( thining ) 현상 등과 같은 문제로 원하는 두께의 산화막을 형성시키는데 근본적인 문제점을 가지고 있다.However, according to the high integration of the device, the LOCOS method has a problem in that the active area is reduced due to the bird's beak phenomenon caused by the side diffusion of oxygen during the device isolation insulating film oxidation process, and the oxide film growth in the narrow area is also reduced. Problems such as field oxide ungrown or thinning of the device isolation oxide film have a fundamental problem in forming an oxide film having a desired thickness.
또한, LOCOS 방법과 PBL 방법은 반도체기판 상부로 볼록한 소자분리절연막을 형성하여 단차를 갖게 됨으로써 후속공정을 어렵게 하는 단점이 있다.In addition, the LOCOS method and the PBL method have a disadvantage in that a subsequent step is difficult by forming a convex element isolation insulating film on the semiconductor substrate and having a step.
이러한 단점을 해결하기 위하여, 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치를 매립한 다음, CMP 방법을 이용하여 상부면을 평탄화시키고, 이러한 평탄화 특성으로 후속공정을 용이하게 실시할 수 있도록 하였다.In order to solve this drawback, the semiconductor substrate is etched to form a trench, and the trench is buried, and then the upper surface is planarized by using the CMP method, and the planarization characteristics can be easily performed in subsequent steps.
도시되지않았으나, 종래기술의 제1실시예에 따른 반도체소자의 소자분리막 형성방법으로서, 트렌치를 매립하는 절연물질로 저압화학기상증착 ( Low PressureChemical Vapor Deposition, 이하에서 LPCVD 이라 함 ) 산화막이나 오존-테오스 대기압화학기상증착 ( O3-TetraEthylOrthoSilicate Atmospheric-Pressure Chemical Vapor Deposition, 이하에서 O3-TEOS APCVD 라 함 ) 을 사용한 예를 설명하면 다음과 같다.Although not shown, a method of forming a device isolation film of a semiconductor device according to a first embodiment of the prior art, comprising a low pressure chemical vapor deposition (LPCVD) as an insulating material filling a trench oxide film or ozone-theo An example of using O3-TetraEthylOrthoSilicate Atmospheric-Pressure Chemical Vapor Deposition (hereinafter referred to as O3-TEOS APCVD) will be described below.
먼저, 반도체기판 상부에 패드산화막을 형성하고, 상기 패드산화막 상부에 질화막을 형성한다.First, a pad oxide film is formed over the semiconductor substrate, and a nitride film is formed over the pad oxide film.
그리고, 소자분리마스크를 이용한 식각공정으로 상기 질화막과 패드산화막 및 일정두께의 반도체기판을 식각하여 상기 반도체기판에 트렌치를 형성한다. 이때, 패턴이 밀집되는 영역에 형성되는 좁은 영역의 소자분리영역은 소폭의 트렌치가 형성되고, 패턴이 형성되지않은 넓은 영역의 소자분리영역은 광폭의 트렌치가 형성된다.In addition, a trench is formed in the semiconductor substrate by etching the nitride layer, the pad oxide layer, and the semiconductor substrate having a predetermined thickness by an etching process using an element isolation mask. At this time, a narrow trench is formed in the device isolation region of the narrow region formed in the region where the pattern is dense, and a wide trench is formed in the device isolation region of the large region where the pattern is not formed.
그 다음에, 상기 트렌치를 매립하는 산화막을 형성하고, 상기 산화막을 CMP 하여 상부면을 평탄하게 형성한다.Next, an oxide film filling the trench is formed, and the oxide film is CMP to form an upper surface flat.
이때, 상기 산화막은 LPCVD 산화막이나 O3-TEOS APCVD 산화막으로 사용한다.In this case, the oxide film is used as an LPCVD oxide film or an O3-TEOS APCVD oxide film.
그러나, 상기 CMP 공정시 상기 폭이 넓은 소자분리영역은 디싱 ( dishing ) 현상을 발생한다.However, in the CMP process, the wide device isolation region generates a dishing phenomenon.
도시되진않았으나, 종래기술의 제2실시예에 따른 반도체소자의 소자분리막 형성방법으로서, 고밀도 플라즈마 화학기상증착 ( High Density Plasma Chemical Vapor Deposition, 이하에서 HDP CVD 라 함 ) 를 트렌치 매립물질로 사용하는 것이다.Although not shown, as a method of forming a device isolation film of a semiconductor device according to a second embodiment of the prior art, high density plasma chemical vapor deposition (hereinafter referred to as HDP CVD) is used as a trench filling material. .
먼저, 반도체기판 상부에 패드산화막을 형성하고, 상기 패드산화막 상부에 질화막을 형성한다.First, a pad oxide film is formed over the semiconductor substrate, and a nitride film is formed over the pad oxide film.
그리고, 소자분리마스크를 이용한 식각공정으로 상기 질화막과 패드산화막 및 일정두께의 반도체기판을 식각하여 상기 반도체기판에 트렌치를 형성한다. 이때, 패턴이 밀집되는 영역에 형성되는 좁은 영역의 소자분리영역은 소폭의 트렌치가 형성되고, 패턴이 형성되지않은 넓은 영역의 소자분리영역은 광폭의 트렌치가 형성된다.In addition, a trench is formed in the semiconductor substrate by etching the nitride layer, the pad oxide layer, and the semiconductor substrate having a predetermined thickness by an etching process using an element isolation mask. At this time, a narrow trench is formed in the device isolation region of the narrow region formed in the region where the pattern is dense, and a wide trench is formed in the device isolation region of the large region where the pattern is not formed.
그 다음에, 상기 트렌치를 매립하는 산화막을 형성한다.Next, an oxide film filling the trench is formed.
이때, 상기 산화막은 HDP CVD 산화막을 형성한 것으로, 아르곤 이온에의한 이방성식각공정과 증착공정이 동시에 실시되며 그 비율은 1 : 3 정도가 된다. 여기서, 상기 HDP CVD 산화막인 산화막은 소폭의 활성영역에는 적게 형성되고, 광폭의 활성영역에는 많이 형성된다.In this case, the oxide film is a HDP CVD oxide film, the anisotropic etching process and the deposition process by argon ions are carried out at the same time, the ratio is about 1: 3. Here, the oxide film, which is the HDP CVD oxide film, is formed in a small amount in the small active region and is formed in the wide active region.
그리고, 상기 산화막을 CMP 하여 상부면을 평탄하게 형성한다. 그러나, 상기 CMP 공정시 상기 광폭의 트렌치가 형성된 부분은 디싱 ( dishing ) 현상을 발생된다.Then, the oxide film is CMP to form a flat top surface. However, in the CMP process, a portion of the wide trench is dished out.
상기한 바와같이 종래기술에 따른 반도체소자의 소자분리막 형성방법은, 트렌치를 매립하는 절연막의 상부면을 평탄하게 형성할 수 없어 후속공정을 어렵게 함으로써 소자분리의 특성을 저하시켜 반도체소자의 수율을 저하시키고 반도체소자의 특성 및 신뢰성을 어렵게 하며 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the method of forming a device isolation film of a semiconductor device according to the prior art, the upper surface of the insulating film filling the trench cannot be formed flat, which makes the subsequent process difficult, thereby degrading device isolation characteristics and lowering the yield of the semiconductor device. In addition, there is a problem in that the characteristics and reliability of the semiconductor device are difficult, and thus high integration of the semiconductor device is difficult.
따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 트렌치를 매립하는 평탄화된 소자분리절연막을 형성하여 후속공정을 용이하게 함으로써 반도체소자의 수율을 향상시키고 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems of the prior art, by forming a flattened device isolation insulating film filling the trench to facilitate the subsequent process to improve the yield of the semiconductor device and improve the characteristics and reliability of the semiconductor device Accordingly, an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device that enables high integration of the semiconductor device.
도 1 은 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.1 is a cross-sectional view showing a method of forming a device isolation film of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 반도체기판 13 : 패드절연막11 semiconductor substrate 13 pad insulating film
15 : 소폭의 트렌치 17 : 광폭의 트렌치15: narrow trench 17: wide trench
19 : 더미패턴, 더미 활성영역 21 : HDP 산화막19: dummy pattern, dummy active area 21: HDP oxide film
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리막 형성방법은,In order to achieve the above object, a device isolation film forming method of a semiconductor device according to the present invention,
반도체기판 상부에 패드절연막을 형성하고 소자분리마스크를 이용한 사진식각공정으로 소폭과 광폭의 트렌치를 형성하되, 상기 광폭의 트렌치 영역에 더미패턴, 즉 더미 활성영역을 정의하는 공정과,Forming a pad insulating film on the semiconductor substrate and forming a narrow and wide trench by a photolithography process using a device isolation mask, defining a dummy pattern, that is, a dummy active region in the wide trench region;
상기 트렌치를 매립하는 HDP 절연막을 전체표면상부에 형성하고 이를 평탄화식각하여 평탄화된 소자분리막을 형성하는 공정을 포함하는 것을 특징으로한다.And forming a planarized device isolation layer by forming an HDP insulating layer filling the trench on the entire surface and planarizing etching the same.
한편, 상기한 목적을 달성하기위한 본 발명의 원리는 다음과 같다.On the other hand, the principle of the present invention for achieving the above object is as follows.
트렌치형 소자분리막의 트렌치 매립용 산화막으로 사용되고 있는 HDP CVD 산화막은 증착 특성상 자기 특성 평탄화 성질이 적절한 더미 크기에서는 우수한 평탄화특성을 보여주고 있으나 그렇지 않은 경우에는 더미로 채워진 기존의 필드 산화막 지역이 최종적으로 더욱 높아져 CMP 공정 이전에 높은 초기 단차를 나타내는 부작용을 일으킨다.The HDP CVD oxide, which is used as the trench fill oxide of the trench isolation device, shows excellent planarization characteristics at the proper dummy size due to the deposition characteristics. Elevated side effects that result in high initial steps prior to the CMP process.
그래서, HDP 증착 특성을 고려한 몇가지 형태의 더미 크기를 고려한 결과 HDP CVD 산화막으로 트렌치 매립을 고려하면서 증착후의 초기 단차를 최소화하기 위해 HDP 증착 특성상 더미패턴 크기가 1 ㎛ 이하가 되어야 한다.Therefore, as a result of considering several types of dummy sizes in consideration of the HDP deposition characteristics, the size of the dummy pattern should be 1 μm or less due to the HDP deposition characteristics in order to minimize the initial step after deposition while considering the trench filling with the HDP CVD oxide film.
따라서, 1.8 × 1.8 ㎛ 정사각형에 0.6 × 0.6 ㎛ 정사각형 구멍이 있는 사각 도너츠형을 갖는 더미패턴을 0.6 ㎛ 간격으로 삽입하고 후속공정으로 HDP CVD 산화막을 형성함으로써 0.6 ㎛ 폭을 갖는 활성영역 위로의 증착은 증착 특성상 산 모양의 증착이 이루어져 CMP 에서의 양호한 연마특성을 충분히 확보할 수 있게 된다.Therefore, by inserting a dummy pattern having a square donut shape with a 0.6 × 0.6 μm square hole in a 1.8 × 1.8 μm square at intervals of 0.6 μm and forming an HDP CVD oxide film in a subsequent process, the deposition over the active area having a width of 0.6 μm is achieved. Due to the deposition characteristics, acid-shaped deposition is performed to ensure sufficient polishing characteristics in CMP.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도이다.1 is a cross-sectional view illustrating a method of forming an isolation layer in a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 패드절연막(13)을 형성한다.First, a pad insulating layer 13 is formed on the semiconductor substrate 11.
그리고, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 패드절연막(13) 및 일정두께의 반도체기판(11)을 식각하여 소폭과 광폭의 트렌치(15,17)를 형성한다.In addition, the pad insulating layer 13 and the semiconductor substrate 11 having a predetermined thickness are etched by an etching process using a device isolation mask (not shown) to form trenches 15 and 17 having a small width and a wide width.
이때, "100" 은 광폭의 트렌치(17)이 형성되는 패턴이 밀집되지않은 영역, 즉 주변회로부를 도시하며, "200" 은 소폭의 트렌치(15)이 형성되는 패턴이 밀집된 영역, 즉 셀부를 도시한다.At this time, "100" shows an area where the pattern of the trench 17 is not densely packed, that is, a peripheral circuit portion, and "200" shows an area where the pattern where the narrow trench 15 is formed is dense, that is, a cell portion. Illustrated.
그리고, 상기 광폭의 트렌치(17)가 구비되는 주변회로부에서 광폭의 트렌치(17) 중앙부에 더미패턴(19), 즉 더미 활성영역을 형성한다.A dummy pattern 19, that is, a dummy active region, is formed in the center of the wide trench 17 in the peripheral circuit portion including the wide trench 17.
여기서, 상기 더미패턴(19)은 트렌치 식각공정에 사용하는 소자분리마스크에 미리 디자인된 것이다.Here, the dummy pattern 19 is designed in advance in the device isolation mask used in the trench etching process.
그리고, 상기 더미패턴(19)은 1.8 × 1.8 ㎛ 정사각형에 0.6 × 0.6 ㎛ 정사각형 구멍이 있는 사각 도너츠형으로 디자인되어 0.6 ㎛ 의 간격으로 디지인된 것이다.The dummy pattern 19 is designed in a square donut shape with a square hole of 0.6 × 0.6 μm in a 1.8 × 1.8 μm square, and is designed in a gap of 0.6 μm.
그 다음, 트렌치(15,17)를 포함한 전체표면상부에 HDP CVD 산화막(21)을 증착한다.Next, an HDP CVD oxide film 21 is deposited on the entire surface including the trenches 15 and 17.
그리고, 상기 HDP CVD 산화막(21)을 CMP 하여 평탄화시킨다. (도 1)Then, the HDP CVD oxide film 21 is planarized by CMP. (Figure 1)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 광폭의 소자분리영역을 갖는 주변회로부에 더미패턴, 즉 더미 활성영역을 형성하고 HDP CVD 산화막을 이용하여 평탄화시킴으로써 디싱현상을 억제하고 그에 따른 반도체소자의 제조공정을 용이하게 하여 반도체소자의 특성 및 신뢰성을 향상시키는 효과를 제공한다.As described above, the method of forming a device isolation film of a semiconductor device according to the present invention suppresses dishing by forming a dummy pattern, that is, a dummy active area, in a peripheral circuit having a wide device isolation region and by planarizing it using an HDP CVD oxide film. And it facilitates the manufacturing process of the semiconductor device thereby provides an effect of improving the characteristics and reliability of the semiconductor device.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100979713B1 (en) * | 2003-07-16 | 2010-09-03 | 매그나칩 반도체 유한회사 | Method of forming an isolation film in semiconductor device |
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| KR970072117A (en) * | 1996-04-24 | 1997-11-07 | 김광호 | Method of planarizing a semiconductor device |
| US5728621A (en) * | 1997-04-28 | 1998-03-17 | Chartered Semiconductor Manufacturing Pte Ltd | Method for shallow trench isolation |
| KR980006047A (en) * | 1996-06-25 | 1998-03-30 | 김광호 | Device Separation Method of Semiconductor Devices |
| JPH1092921A (en) * | 1996-08-21 | 1998-04-10 | Motorola Inc | Integrated circuit having dummy structures and method of forming the same |
| US5923993A (en) * | 1997-12-17 | 1999-07-13 | Advanced Micro Devices | Method for fabricating dishing free shallow isolation trenches |
| US5976949A (en) * | 1997-03-04 | 1999-11-02 | Winbond Electronics Corp. | Method for forming shallow trench isolation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970072117A (en) * | 1996-04-24 | 1997-11-07 | 김광호 | Method of planarizing a semiconductor device |
| KR980006047A (en) * | 1996-06-25 | 1998-03-30 | 김광호 | Device Separation Method of Semiconductor Devices |
| JPH1092921A (en) * | 1996-08-21 | 1998-04-10 | Motorola Inc | Integrated circuit having dummy structures and method of forming the same |
| US5976949A (en) * | 1997-03-04 | 1999-11-02 | Winbond Electronics Corp. | Method for forming shallow trench isolation |
| US5728621A (en) * | 1997-04-28 | 1998-03-17 | Chartered Semiconductor Manufacturing Pte Ltd | Method for shallow trench isolation |
| US5923993A (en) * | 1997-12-17 | 1999-07-13 | Advanced Micro Devices | Method for fabricating dishing free shallow isolation trenches |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100979713B1 (en) * | 2003-07-16 | 2010-09-03 | 매그나칩 반도체 유한회사 | Method of forming an isolation film in semiconductor device |
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