KR920009365B1 - Manufacturing method of bipolar transistor - Google Patents

Manufacturing method of bipolar transistor Download PDF

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KR920009365B1
KR920009365B1 KR1019900006528A KR900006528A KR920009365B1 KR 920009365 B1 KR920009365 B1 KR 920009365B1 KR 1019900006528 A KR1019900006528 A KR 1019900006528A KR 900006528 A KR900006528 A KR 900006528A KR 920009365 B1 KR920009365 B1 KR 920009365B1
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South Korea
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silicon nitride
oxide film
nitride film
film
cvd oxide
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KR1019900006528A
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Korean (ko)
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KR910020815A (en
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노태훈
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금성일렉트론주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices

Abstract

The bipolar transistor is mfd. by (a) forming a burial layer (2), an epitaxial layer (3) and a field oxide film (4) on the substrate (1), (b) forming a silicon nitride film (5), a CVD oxide film (6), a silicon nitride film (7) and a CVD oxide film (8) on the film (4) and the layer (3) in order, (c) plasma-etching the films (5,6,7,8) to form an external base region, and then implanting a high concn. boron ion into the region, and (d) etching the film (5) of a collector region, depositing a polycrystal silicon (9), and then doping a phosphorus on the region. The transistor has a submicron emitter width.

Description

바이폴라 트랜지스터의 제조방법Manufacturing method of bipolar transistor

제1도는 종래의 제조공정을 나타낸 단면도.1 is a cross-sectional view showing a conventional manufacturing process.

제2도는 본 발명의 제조공정을 나타낸 단면도.2 is a cross-sectional view showing a manufacturing process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 기판 2 : 매몰층1 substrate 2 buried layer

3 : 에피텍셜층 4 : 필드 산화막3: epitaxial layer 4: field oxide film

5, 7 : 실피콘 질화막 6, 8 : CVD산화막5, 7: silicon nitride film 6, 8: CVD oxide film

9 : 다결정 실리콘 10 : 금속9: polycrystalline silicon 10: metal

본 발명은 서브-미크론(Sub-Micron)에미터 폭을 갖는 바이폴라 트랜지스터의 제조방법에 관한 것이다. 종래에는 바이폴라 트랜지스터를 제조하기 위하여 제1a도에 도시된 바와 같이 P형기판(1)에 n+매몰층(2)과 에피텍셜층(3)을 형성하고 산화막 (11)을 성장시킨 상태에서 P+이온을 주입하여 소자격리를 위한 격리층(12)을 형성하였으며, 이어b도와 같이 마스킹 및 에칭 후 붕소(Boron) 확산 공정을 행하여 에이스영역을 형성하였다. 그리고 c도와 같이 다시 마스킹 및 에칭 수 인(Phosphorus)확산 공정을 행하여 에미터/콜렉터 영역을 형성하고 통상의 금속증착(Metallization)공정을 실시하므로 바이폴라 트랜지스터를 제조하였다. 그러나, 상기와 같은 종래의 기술에 있어서는 PN접합 소자격리를 이용 하므로 소자의 면적을 줄이는데 한계가 있고 소자 자체에 존재하는 저항성분과 기생 커패시턴스 성분때문에 고속동작 특성을 얻기가 어려 웠다. 따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위한 것으로 이를 첨부된 도면 제2도에 의하여 상세히 다음과 같다. 먼저, 본 발명에서의 소자격리 이전 공정은 기존 공정과 같으며 이때의 소자겨리 방법 역시 통상의 로코스(LOCOS)공정기술을 이용한다. 즉, a도와 같이 기판(1)에 매몰층(2)과 에피택셜층(3) 및 로코스 공정에 의한 필드산화막(4)을 형성하여 소자간의 격리를 행하고 이어서 실리콘 질화막(5), CVD산화막(6), 실리콘질화막(7), CVD산화막(8)을 차례로 형성한다. 이때, CVD산화막(8)이 CVD산화막(6)보다 두꺼워야하고 실리콘 질화막(6)이 실리콘 질화막(5)보다는 얇아야 한다. 다음에 b도와 같이 플라즈마 식각방법으로 실리콘 질화막(5)(7)가 CVD산화막 (6)(8)을 선택적으로 제거하여, 외부 베이스영역을 형성한 후 붕소이온을 고농도(P++)로 주입한다. 그리고, c도와 같이 최상단의 CVD산화막(8)을 식각하면 실리콘질화막( 5)(7) 사이의 CVD산화막(6)에도 동시에 측면식각이 이루어 진다.The present invention relates to a method of manufacturing a bipolar transistor having a sub-micron emitter width. Conventionally, in order to manufacture a bipolar transistor, as shown in FIG. 1A, an N + buried layer 2 and an epitaxial layer 3 are formed on a P-type substrate 1, and P + ions are grown in a state where an oxide film 11 is grown. The isolation layer 12 was formed by isolating the device, and an ace region was formed by performing a boron diffusion process after masking and etching as shown in FIG. Then, as shown in c, the bipolar transistor was manufactured by performing masking and etching Phosphorus diffusion process to form an emitter / collector region and performing a general metallization process. However, in the conventional technology as described above, since the isolation of the PN junction device is used, there is a limit in reducing the area of the device, and it is difficult to obtain high-speed operation characteristics due to the resistance component and parasitic capacitance component present in the device itself. Accordingly, the present invention is to solve the conventional problems as described above in detail by the accompanying drawings, Figure 2 as follows. First, the device isolation process in the present invention is the same as the existing process and the device isolation method at this time also uses a conventional LOCOS process technology. That is, as shown in a, the buried layer 2, the epitaxial layer 3, and the field oxide film 4 by the LOCOS process are formed on the substrate 1 to isolate the devices, and then the silicon nitride film 5 and the CVD oxide film. (6), silicon nitride film 7 and CVD oxide film 8 are formed in this order. At this time, the CVD oxide film 8 should be thicker than the CVD oxide film 6 and the silicon nitride film 6 should be thinner than the silicon nitride film 5. Next, as shown in b, the silicon nitride film 5, 7 selectively removes the CVD oxide film 6, 8 by plasma etching, and forms boron ions at a high concentration (P ++ ) after forming an external base region. do. When the topmost CVD oxide film 8 is etched as shown in c, side etching is simultaneously performed on the CVD oxide film 6 between the silicon nitride films 5 and 7.

이후, d도와 같이 상단의 실콘 질화막(7)을 식각하고 최하단의 실리콘 질화막 (5)을 식각한 후 이온 주입방법으로 붕소이온을 주입한다. 그리고, e도와 같이 CVD산화막(6)을 식각하고 산화공정을 실시한 후 f도와 같이 내부 베이스 영역의 실리콘 질화막(5)을 식각하고 다시 붕소이온을 주입한다. 다음에 g도와 같이 콜렉터 영역의 실리콘질화막(5)을 식각하고 다결정 실리콘(9)을 증착시킨 후 인을 도핑한다. 그리고 h도와 같이 금속(10) 전극형성을 위한 콘텍트 사진/식각 공정후 금속증착 공정을 행하며, 이후의 공정은 기존의 공정과 같이 실시한다. 이상과 같은 공정에 의해 제조되는 본 발명은 베이스 영역에서 측면으로 P, P+, P++의 농도차이를 갖게되어 높은 전압에소도 동작이 가능함은 물론 실리콘 질화막(5)(7)과 다결정 실리콘(6)(8)으로 구성되는 4층구조를 이용하므로 모스 소자 구성이 가능하며 바이폴라-모스 소자의 제조에도 적용시킬 수 있으며 기존의 공정으로 서브-미크론 패턴 형성이 가능할 뿐만 아니라 특히 소자면적의 감소로 인하여 직접도를 증가시킬 수 있음과 아울러 기생효과의 감소로 인한 고속동작 특성을 얻을 수 있는 장점이 있다.Thereafter, as shown in d, the silicon nitride film 7 at the top is etched and the silicon nitride film 5 at the bottom is etched, and boron ions are implanted by an ion implantation method. Then, the CVD oxide film 6 is etched and the oxidation process is performed as shown in e, and the silicon nitride film 5 in the inner base region is etched as shown in f, and boron ions are implanted again. Next, as shown in g, the silicon nitride film 5 in the collector region is etched and polycrystalline silicon 9 is deposited, and then phosphorus is doped. Then, as shown in FIG. 9, the metal deposition process is performed after the contact photo / etching process for forming the metal 10 electrode, and the subsequent process is performed as in the existing process. The present invention manufactured by the above process has a difference in concentration of P, P + , P ++ from the base region to the side, and can operate even at a high voltage, as well as silicon nitride films 5 and 7 and polycrystalline silicon. The four-layer structure consisting of (6) and (8) enables the formation of MOS devices, and can be applied to the production of bipolar-MOS devices, as well as the formation of sub-micron patterns by conventional processes, and in particular, the reduction of device area. Due to this, the directness can be increased and the high speed operation characteristic can be obtained due to the reduction of the parasitic effect.

Claims (2)

기판(1)에 매몰층(2)과 에피택셜층(3) 및 필드산화막(4)을 형성한 것에 있어서, 상기위에 실리콘 질화막(5), CVD산화막(6), 실리콘 질화막(7), CVD(8)을 차례로 형성하고 플즈마 식각 방법으로 외부 베이스영역을 형성한 후 고농도의 붕소이온을 주입하며, 최상단의 CVD산화막(8)을 식각하여 CVD산화막(6)에 동시에 측면 식각이 이루어지게하고, 실리콘 질화막(7)을 식각한 후 실리콘 질화막(5)을 식각하여 붕소이온을 주입며, CVD산화막(6)을 식각하고 산화공정후 내부베이스 영영의 실리콘 질화막( 5)을 식각하여 붕소이온을 주입하고, 콜렉터 영역의 실리콘 질화막(5)을 식각고 다결정실리콘(9)을 증착시킨 후 인을 도핑함을 특징으로하는 바이폴라 트랜지스터의 제조방법.In the formation of the buried layer 2, the epitaxial layer 3 and the field oxide film 4 on the substrate 1, the silicon nitride film 5, the CVD oxide film 6, the silicon nitride film 7, and the CVD on the substrate 1 (8) are formed in order, an external base region is formed by a plasma etching method, and then a high concentration of boron ions are implanted, and the top CVD oxide film 8 is etched to simultaneously laterally etch the CVD oxide film 6. After the silicon nitride film 7 is etched, the silicon nitride film 5 is etched to inject boron ions, the CVD oxide film 6 is etched, and after the oxidation process, the boron ions are etched by etching the inner nitrided silicon nitride film 5. Implanting, etching the silicon nitride film (5) in the collector region, depositing polysilicon (9), and doping phosphorus. 제1항에 있어서, CVD산화막(8)을 CVD산화막(6)보다 두껍게 형성함과 아울러 실리콘 질화막(7)을 실리콘 질화막(5)보다 얇게 형성함을 특징으로하는 바이폴라 트랜지스터의 제조방법.The method of manufacturing a bipolar transistor according to claim 1, wherein the CVD oxide film (8) is formed thicker than the CVD oxide film (6) and the silicon nitride film (7) is formed thinner than the silicon nitride film (5).
KR1019900006528A 1990-05-09 1990-05-09 Manufacturing method of bipolar transistor KR920009365B1 (en)

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