KR950002200B1 - Mosfet and manufacturing method thereof - Google Patents
Mosfet and manufacturing method thereof Download PDFInfo
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- KR950002200B1 KR950002200B1 KR1019920012597A KR920012597A KR950002200B1 KR 950002200 B1 KR950002200 B1 KR 950002200B1 KR 1019920012597 A KR1019920012597 A KR 1019920012597A KR 920012597 A KR920012597 A KR 920012597A KR 950002200 B1 KR950002200 B1 KR 950002200B1
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- gate
- forming
- insulating film
- semiconductor layer
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- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 230000015556 catabolic process Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract 3
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Abstract
Description
제 1 도는 종래의 MOSFET 구조단면도.1 is a cross-sectional view of a conventional MOSFET structure.
제 2 도는 본 발명의 MOSFET 구조단면도.2 is a cross-sectional view of a MOSFET structure of the present invention.
제 3 도는 본 발명의 MOSFET 공정단면도.Figure 3 is a MOSFET process cross section of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : p형 실리콘기판 2 : 게이트 절연막1: p-type silicon substrate 2: gate insulating film
3 : 폴리실리콘 5 : 측벽절연막3: polysilicon 5: sidewall insulating film
6 : 소오스/드레인 7 : p형 웰6 source / drain 7 p-type well
8 : 필드산화막 9 : CVD 산화막8: field oxide film 9: CVD oxide film
10 : 금속층10: metal layer
본 발명은 MOSFET(Metal Oxide Semiconductor Field Effect Transistor)에 관한 것으로, 특히 고집적 소자에 적당한 셀프-얼라인드 컨벡스(Self aligned convex) MOSFET의 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal oxide semiconductor field effect transistor (MOSFET), and more particularly, to a structure and a manufacturing method of a self-aligned convex MOSFET suitable for highly integrated devices.
종래의 MOSFET를 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the conventional MOSFET with reference to the accompanying drawings as follows.
제 1 도는 종래의 MOSFET 구조단면도로써, p형 실리콘기판(1)의 표면에 게이트 절연막(2)을 형성하고, 그위에 폴리실리콘(3)과 캡게이트 절연막(4)을 차례로 증착하고 포토 에치 공정으로 패터닝하여 게이트를 형성하고, 게이트를 마스크로 하여 실리콘기판(1)에 LDD 구조를 위한 저농도 n형 이온주입하고, 게이트 측벽에 측벽절연막(5)을 형성하여 고농도 n형 이온주입으로 LDD 구조의 소오스/드레인(6)을 형성하여 이루어진 MOSFET 구조이다.FIG. 1 is a cross-sectional view of a conventional MOSFET structure, in which a gate insulating film 2 is formed on a surface of a p-type silicon substrate 1, a polysilicon 3 and a cap gate insulating film 4 are sequentially deposited thereon, and a photo etch process. Patterned to form a gate, a low concentration n-type ion implantation for the LDD structure is implanted into the silicon substrate 1 using the gate as a mask, and a sidewall insulating film 5 is formed on the sidewall of the gate to form a LDD structure with a high concentration n-type ion implantation. It is a MOSFET structure formed by forming the source / drain 6.
이와같은 종래의 MOSFET는 게이트에 전압을 인가하면 게이트 하측의 소오스/드레인 사이에 채널이 형성되어 신호를 전달하게 된다.In the conventional MOSFET, when a voltage is applied to a gate, a channel is formed between a source / drain under the gate to transmit a signal.
그러나 이와같은 종래의 MOSFET에 있어서는 낮은 전압(5V-3.3V)에 의한 디자인 마진(Design Margin)이 감소하고, 숏 채널 효과(Short channel effect)에 의한 펀치쓰루(Punch-through)의 항복 전압을 개선하기 위해서는 기판농도가 증가해야 하며, 기판 농도의 증가에 따라 문턱전압(VT)을 조절하기 위해 게이트 절연막을 얇게 형성해야 하는 문제점이 발생하며 게이트 절연막을 얇게 형성하게 되면 GIDL(Gate Induced Drain Leakage)와 TDDB(Time Dependent Dielectric Breakdown) 등의 새로운 문제점들이 계속해서 발생된다.However, in such a conventional MOSFET, the design margin due to low voltage (5V-3.3V) is reduced and the punch-through breakdown voltage due to the short channel effect is improved. In order to increase the substrate concentration, a problem arises in that a thin gate insulating film is formed to control the threshold voltage (V T ) according to the increase of the substrate concentration. And new problems continue to arise, such as TDDB (Time Dependent Dielectric Breakdown).
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로, 3차원적으로 채널길이를 확장하여 고집적화에 따른 숏 채널 효과를 극복한 고집적 반도체 소자의 구조 및 제조방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a structure and a manufacturing method of a highly integrated semiconductor device overcoming the short channel effect due to high integration by extending the channel length in three dimensions.
이와같은 목적을 달성하기 위한 본 발명은 채널영역을 볼록하게 형성하고 게이트가 상기 볼록한 부위를 감싸도록 형성하고 문턱전압과 항복전압을 별도의 이온주입으로 개선한 것이다.The present invention for achieving the above object is to form a convex channel region, the gate is formed to surround the convex portion and to improve the threshold voltage and breakdown voltage by separate ion implantation.
이와같은 본 발명을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.This invention is described in more detail with reference to the accompanying drawings as follows.
제 2 도는 본 발명의 MOSFET 구조단면도로써, p형 실리콘기판(1)의 p형 웰(well)(7)내에 LDD구조의 n형 소오스/드레인(6)이 형성되고, 소오스/드레인간의 채널영역이 볼록하게 형성되고, 볼록한 채널영역 표면에 게이트 절연막(2)이 형성되고, 볼록한 채널영역을 감싸고 게이트(3)가 형성된 구조이다.2 is a cross-sectional view of the MOSFET structure of the present invention, in which an n-type source / drain 6 having an LDD structure is formed in a p-type well 7 of a p-type silicon substrate 1, and a channel region between the source and the drain is formed. The structure is formed convexly, the gate insulating film 2 is formed on the surface of the convex channel region, surrounds the convex channel region, and the gate 3 is formed.
이와같은 구조의 본 발명 MOSFET 제조방법을 공정 단면도인 제 3 도를 참조하여 설명하면 다음과 같다.Referring to FIG. 3, which is a cross-sectional view of the present invention, the MOSFET manufacturing method having such a structure is as follows.
먼저 제 3도a와 같이 p형 실리콘기판(1)에 p형 웰(Well)(7)을 형성하고 게이트 마스크를 이용하여 채널 영역을 제외한 p형 웰(7)영역을 소정의 깊이로 식각한다.First, as shown in FIG. 3A, a p-type well 7 is formed in the p-type silicon substrate 1, and the p-type well 7 region excluding the channel region is etched to a predetermined depth using a gate mask. .
먼저 제 3 도b와 같이 소자간의 격리를 위해 필드산화막(8)을 성장하고 액티브영역에 게이트 산화막(2a)을 성장하고 문턱전압(VT)조절과 항복전압 개선을 위해 p형 웰(7) 표면부위와 깊은 부분에 이온 주입을 실시한다.First, FIG. 3 for element isolation between the growth of the field oxide film 8, and growing a gate oxide film (2a) on the active region and the threshold voltage as b (V T), control the breakdown-voltage p-type to improve the well (7) Ion implantation is performed on the surface and deep parts.
이때, 채널영역은 DSC(Drain Separated Channel Implat)가 된다.At this time, the channel region becomes DSC (Drain Separated Channel Implat).
그리고, 제 3 도c와 같이 전면에 도핑된 폴리실리콘(3)을 증착하거나 폴리실리콘(3)을 증착하여 도핑을 한뒤 폴리실리콘(3)위 전면에 CVD(Chemical Vapour Deposition) 산화막(9)을 묽게 증착하여 평탄화시킨다.Then, as shown in FIG. 3C, the doped polysilicon 3 is deposited on the front surface or the polysilicon 3 is deposited to doping, and then a CVD (Chemical Vapor Deposition) oxide film 9 is deposited on the front surface of the polysilicon 3. Dilute thin to planarize.
계속해서, 제 3 도d와 같이 CVD 산화막(9)을 채널 영역 상측의 폴리실리콘(3)이 들어날 때까지 에치백하고, 들어난 표면에 텅스텐(W)을 증착하거나 에치백후 고융점 금속을 증착하고 어닐링하여 폴리실리콘(3) 표면에 실리사이드(silicide)를 형성하는 방법으로 금속층(10)을 형성한다.Subsequently, as shown in FIG. 3D, the CVD oxide film 9 is etched back until the polysilicon 3 above the channel region enters, and tungsten (W) is deposited on the raised surface or the high melting point metal is etched back. The metal layer 10 is formed by depositing and annealing to form silicide on the surface of the polysilicon 3.
제 3 도e와 같이 CVD 산화막(9)을 완전히 제거하고 수직 식각하여 폴리실리콘(3)의 불필요한 부위를 제거하여 게이트를 패터닝한 뒤 LDD 구조의 소오스/드레인을 형성하기 위해 저농도 n형 이온 주입을 한다.As shown in FIG. 3E, the CVD oxide layer 9 is completely removed and vertically etched to remove unnecessary portions of the polysilicon 3 to pattern the gate, and then a low concentration n-type ion implantation is performed to form a source / drain of LDD structure. do.
그다음, 제 3 도f와 같이 게이트에 측벽산화막을 형성하고, 고농도 n형 이온주입하여 LDD 구조의 소오스/드레인(6)을 형성함으로 본 발명의 MOSFET가 완성된다.Then, the MOSFET of the present invention is completed by forming a sidewall oxide film in the gate and implanting a high concentration of n-type ions to form the source / drain 6 of the LDD structure as shown in FIG.
이상에서 설명한 바와같은 본 발명의 MOSFET에 있어서는 2차원적으로는 동일한 채널 길이를 가지면서 3차원적으로 채널길이 확장이 가능하며 전원전압(Vcc)이 높아도 전류동작(circuit operation)이 가능하므로 디자인 마진이 크게되고, p형 웰 표면과 깊은 영역에 이온 주입하여 문턱 전압조절과 펀치 쓰루에 의한 항복전압 개선을 별도로 조정할 수 있으며, 게이트 절연막의 두께를 얇게 할 필요가 없어 TDDB, GIDL등의 문제점을 해결할 뿐만 아니라 기타 디램(DRAM)의 커패시터와 함께 형성될 경우 셀 커패시턴스(cell capacitance)를 증가시킬 수 있는 등의 효과가 있다.As described above, in the MOSFET of the present invention, the channel length can be expanded in three dimensions while having the same channel length in two dimensions, and a circuit operation can be performed even when the power supply voltage Vcc is high. Larger, ion implantation into the p-type well surface and deeper areas allows the adjustment of threshold voltage and breakdown voltage improvement due to punch-through separately. In addition, when formed with other DRAM capacitors, the cell capacitance may be increased.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920012597A KR950002200B1 (en) | 1992-07-15 | 1992-07-15 | Mosfet and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920012597A KR950002200B1 (en) | 1992-07-15 | 1992-07-15 | Mosfet and manufacturing method thereof |
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| Publication Number | Publication Date |
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| KR940003095A KR940003095A (en) | 1994-02-19 |
| KR950002200B1 true KR950002200B1 (en) | 1995-03-14 |
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| KR1019920012597A KR950002200B1 (en) | 1992-07-15 | 1992-07-15 | Mosfet and manufacturing method thereof |
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| KR100260488B1 (en) * | 1996-12-30 | 2000-07-01 | 김영환 | Method of manufacturing a field effect transistor |
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