KR940004414B1 - Structure and making method of semiconductor device - Google Patents
Structure and making method of semiconductor device Download PDFInfo
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- KR940004414B1 KR940004414B1 KR1019910011714A KR910011714A KR940004414B1 KR 940004414 B1 KR940004414 B1 KR 940004414B1 KR 1019910011714 A KR1019910011714 A KR 1019910011714A KR 910011714 A KR910011714 A KR 910011714A KR 940004414 B1 KR940004414 B1 KR 940004414B1
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- South Korea
- Prior art keywords
- polysilicon
- oxide film
- conductive
- semiconductor device
- substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims description 6
- 239000010408 film Substances 0.000 claims 8
- 238000000151 deposition Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 239000010409 thin film Substances 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
제1도는 종래 반도체 소자의 공정단면도.1 is a process cross-sectional view of a conventional semiconductor device.
제2도는 본 발명 반도체 소자의 공정단면도.2 is a process cross-sectional view of a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2, 5 : 산화막1 substrate 2, 5 oxide film
3 : 질화막 4 : 폴리실리콘3: nitride film 4: polysilicon
6 : P/R 7, 8 : 도핑영역6: P / R 7, 8: doping area
본 발명은 반도체 소자의 구조 및 제조방법에 관한 것으로 특히 필드산화막을 성장시켜 별도의 필드영역을 형성하지 않고 전자가 주입된 플로우팅(Floating) 게이트를 이용하여 소오스/드레인영역 사이를 절연시켜 줄수 있도록 한 것이다.The present invention relates to a structure and a manufacturing method of a semiconductor device. In particular, a field oxide film may be grown to insulate between source / drain regions using a floating gate in which electrons are injected without forming a separate field region. It is.
종래 반도체 소자의 제조공정은 제1a도에 도시된 바와 같이 P형 기판(1)위에 베이스 산화막(2)과 질화막(3)을 증착하고 마스킹(Masking)공정에 의해 상기 질화막(3)중에서 필드영역을 형성할 부분의 질화막을 선택적으로 에치한다.In the manufacturing process of the conventional semiconductor device, as shown in FIG. 1A, the base oxide film 2 and the nitride film 3 are deposited on the P-type substrate 1, and the field region in the nitride film 3 is formed by a masking process. The nitride film of the portion to be formed is selectively etched.
그리고, 전표면에 P형 이온(예를 들어 보론)을 주입하여 질화막이 제거된 부분의 기판(1)내부로 P형 이온이 침투되게 하므로 P형 도핑영역(9)을 형성한다.P-type ions (for example, boron) are implanted into the entire surface to allow P-type ions to penetrate into the substrate 1 in the portion where the nitride film is removed, thereby forming the P-type doped region 9.
다음에 제1b도와 같이 필드산화를 실시하여 상기 P형 도핑영역(9)위에 필드산화막(10)을 형성하고 질화막(3)을 제거한다.Next, as shown in FIG. 1B, field oxidation is performed to form a field oxide film 10 on the P-type doped region 9 and to remove the nitride film 3.
이어서 제1c도와 같이 N형 이온(예를 들어 비소, 인)을 주입하여 필드산화막(10)이외의 액티브 영역에 N+형 도핑영역(7)(8)을 형성한다.Subsequently, as illustrated in FIG. 1C, N type ions (for example, arsenic and phosphorus) are implanted to form N + type doped regions 7 and 8 in the active region other than the field oxide film 10.
상기와 같은 종래 반도체 소자에 있어서는 두꺼운 필드산화막(10)과 그 밑에 P형 하이(High) 도핑영역(9)을 형성하여 높은 임계전압을 유지하기 때문에 필드산화막(10)을 성장시킬때 질화막(3) 스트레스(stress) 및 산화막(2)에 의해 결합이 발생되기 쉬우며 불순물의 하이 도핑으로 인한 누설전류(Leakage Current)가 증가하고 항복전압(Breakdown Voltage)의 감소로 인하여 소자가 파괴되기 쉬우며 필드영역에 접하는 정션 커패시턴스가 증가하게 되는 결점이 있다.In the conventional semiconductor device as described above, since the thick field oxide film 10 and the P-type high doping region 9 are formed thereunder to maintain a high threshold voltage, the nitride film 3 is grown when the field oxide film 10 is grown. ) Coupling is easily caused by stress and oxide film 2, and leakage current is increased due to high doping of impurities, and device is easily destroyed due to decrease of breakdown voltage. There is a drawback that the junction capacitance near the area is increased.
본 발명은 이와 같은 종래의 제반 결점을 해결하기 위한 것으로 필드영역을 별도로 성장시키기 않고 액티브와 액티브 영역사이에 전하를 갖는 플로우팅 게이트(Floating Gate)를 형성하여 상기와 같은 소자의 결함을 보완할수 있는 반도체 소자의 구조와 제조방법을 제공하는데 그 목적이 있다.The present invention is to solve the above-mentioned general drawbacks to form a floating gate having a charge between the active and the active region without growing the field region separately to compensate for the defects of the device as described above. Its purpose is to provide a structure and a manufacturing method of a semiconductor device.
이하에서 상기와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제2도에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.
본 발명은 먼저 제2a도와 같이 P형 규소기판(1)위에 산화막(2)과 질화막(3) 및 폴리실리콘(4)을 차례로 증착하고 마스킹 공정에 의해 상기 폴리실리콘(4)을 식각하여 필드영역을 이룰 부분의 폴리실리콘만 남게한다.The present invention first deposits an oxide film (2), a nitride film (3), and a polysilicon (4) on a P-type silicon substrate (1) as shown in FIG. 2A, and then etches the polysilicon (4) by a masking process. Only the polysilicon of the part to be made is left.
그리고 제2b도와 같이 산화막(5)을 증착하고 패터닝하여 산화막(5)에 의해 폴리실리콘(4) 상면과 측벽이 둘러쌓이도록 한다.As illustrated in FIG. 2B, the oxide film 5 is deposited and patterned so that the top surface and the sidewalls of the polysilicon 4 are surrounded by the oxide film 5.
이러한 상태에서 전자(Electron)를 주입하여 상기 폴리실리콘(4)에 전자가 차아지-업(Charge-up)되게 하는데 이때 주입된 전자가 상기 산화막(5)을 뚫고 들어가 폴리실리콘(4) 내부에 존재하게 되며 폴리실리콘(4)내에 존재하는 전자는 산화막(5)에 의해 보존된다.In this state, electrons are injected to charge electrons to the polysilicon 4, and the injected electrons penetrate the oxide film 5 and enter the inside of the polysilicon 4. Electrons present in the polysilicon 4 are preserved by the oxide film 5.
또한, 폴리실리콘(4)내에 존재하는 전자는 폴리실리콘(4)이 플로우팅 게이트 역할을 하여 기판(1)에 홀(hole)을 유발시킴으로써 이 부분의 임계전압(VT)을 높이게 된다.In addition, electrons present in the polysilicon 4 cause the polysilicon 4 to act as a floating gate to cause a hole in the substrate 1, thereby increasing the threshold voltage V T of this portion.
그리고, 폴리실리콘(4)이외의 영역은 질화막(3)에 의해 블로킹(Blocking)되어 전자가 기판(1)으로 침투하지는 못하게 된다.In addition, the regions other than the polysilicon 4 are blocked by the nitride film 3 so that electrons do not penetrate into the substrate 1.
다음에 제2c도와 같이 마스킹 공정에 의해 액티브 영역의 산화막(2)과 질화막(3)을 제거하고 제2d도와 같이 P/R을 형성한후 패터닝하여 폴리실리콘(4) 상방에만 P/R(6)이 남도록 한다.Next, as shown in FIG. 2C, the oxide film 2 and the nitride film 3 in the active region are removed by a masking process, and P / R is formed as shown in FIG. 2D, and then patterned to form P / R (6) only above the polysilicon 4 ).
이 상태에서 N형 이온(예를 들어 As또는 P)을 주입하여 액티브 영역에 소오스와 드레인을 이루기 위한 N+도핑영역(7)(8)을 형성하며 이때 P/R(6)에 의해 N형 이온이 폴리실리콘(4) 내부로 침투하지 않게 되어 폴리실리콘(4) 내부에 존재하는 전자와 중화되는 것을 방지하게 된다.In this state, N + ions (for example, A s or P) are implanted to form N + doped regions 7 and 8 for forming a source and a drain in the active region, whereby N is formed by P / R 6. Form ions are prevented from penetrating into the polysilicon 4 and neutralizing with electrons present in the polysilicon 4.
따라서, 상기와 같이 반도체 소자를 제조하면 폴리실리콘(4) 내부에 존재하는 전자에 의하여 N+도핑영역(7)(8)사이의 채널부분에 홀이 축적되어(hole accumulation) N+도핑영역(7)(8)사이를 절연시켜 주므로 기존의 필드영역의 역할을 하게 되는 것이다.Therefore, when the semiconductor device is manufactured as described above, holes are accumulated in the channel portion between the N + doped regions 7 and 8 by electrons existing in the polysilicon 4, and thus the N + doped region ( It insulates between 7) (8), so it acts as an existing field area.
이상에서 설명한 바와 같은 본 발명은 필드영역을 이루기 위한 별도의 필드산화막을 성장시킬 필요가 없으므로 질화막이 스트레스를 받는 현상을 제거할 수 있으며, 격리영역, 즉 필드영역에 불순물을 하이 도핑시킬 필요가 없어 누설전류를 감소시킬 수 있다.As described above, the present invention does not need to grow a separate field oxide film for forming a field region, thereby eliminating the stress of the nitride layer, and does not need to high-dope impurities in an isolation region, that is, a field region. Leakage current can be reduced.
또한, 정선의 항복전압을 증가시킬수 있어 소자가 파괴되는 것을 방지할 수 있고 필드여역에 접하는 정션 커패시턴스를 감소시킬수 있는 효과가 있다.In addition, since the breakdown voltage of the line can be increased, the device can be prevented from being destroyed and the junction capacitance in contact with the field region can be reduced.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910011714A KR940004414B1 (en) | 1991-07-10 | 1991-07-10 | Structure and making method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910011714A KR940004414B1 (en) | 1991-07-10 | 1991-07-10 | Structure and making method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930003295A KR930003295A (en) | 1993-02-24 |
| KR940004414B1 true KR940004414B1 (en) | 1994-05-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910011714A KR940004414B1 (en) | 1991-07-10 | 1991-07-10 | Structure and making method of semiconductor device |
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|---|---|
| KR (1) | KR940004414B1 (en) |
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1991
- 1991-07-10 KR KR1019910011714A patent/KR940004414B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR930003295A (en) | 1993-02-24 |
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