JPS61107756A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS61107756A JPS61107756A JP59227727A JP22772784A JPS61107756A JP S61107756 A JPS61107756 A JP S61107756A JP 59227727 A JP59227727 A JP 59227727A JP 22772784 A JP22772784 A JP 22772784A JP S61107756 A JPS61107756 A JP S61107756A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- deep hole
- semiconductor substrate
- capacitor
- electric field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
Landscapes
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は高集積化が可能なキャパシタや素子間分離領域
に係り、特に半導体基板に深孔を形成し上記半導体装置
を実現する技術に好適な絶縁酸化膜に関するものである
。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a capacitor and an element isolation region that can be highly integrated, and is particularly suitable for a technique for forming deep holes in a semiconductor substrate to realize the above semiconductor device. This relates to an insulating oxide film.
溝キャパシタの絶縁耐圧については、第３１回応用物理
学関係連合講演会予講集、第４６０頁、１９８４年にお
ける森江、峯岸及び中高による［熱酸化膜を用いた溝キ
ャパシタの容量および耐圧」と題する報告において論じ
られている。溝エツジ部分で熱酸化膜が薄くなり、絶縁
耐圧が低下する問題は、１）＠化温度を上げ酸化膜の粘
性流動により溝エツジ部での酸化膜厚の減少を押える。Regarding the dielectric strength voltage of groove capacitors, see "Capacity and breakdown voltage of groove capacitors using thermal oxide film" by Morie, Minegishi, and Nakataka, 1984, 31st Applied Physics Conference Preliminary Lectures, p. 460. Discussed in the report titled. The problem of thinning of the thermal oxide film at the trench edge and lowering of the dielectric strength is as follows: 1) Raise the oxidation temperature and suppress the reduction in the oxide film thickness at the trench edge due to the viscous flow of the oxide film.
２）熱酸化膜厚を薄くしエツジ部での応力を押え、酸化
膜厚減少を押える。ことにより解決できると報告されて
いる。2) Reduce the thickness of the thermal oxide film to suppress the stress at the edges and prevent the reduction in oxide film thickness. It is reported that this can be solved by
しかし、この方法は、高温度での熱処理を行なって酸１
ヒ膜の膜厚減少を防止しており、将来、微細化がさらに
進んだ場合、ＰＮ接合など、他の部分への影響を防止し
つつ、酸化膜の膜厚を効果的に抑促Ｔし得る低温度の処
理法が必要となる可能性が大きく、このような低温処理
法が、半導体装置の微細化に有効になると考えられる。However, this method requires heat treatment at high temperatures to
This prevents the thickness of the oxide film from decreasing, and if further miniaturization progresses in the future, it will effectively suppress the thickness of the oxide film while preventing effects on other parts such as PN junctions. There is a strong possibility that a low-temperature processing method will be needed to achieve this goal, and it is thought that such a low-temperature processing method will be effective in miniaturizing semiconductor devices.
（発明の目的〕 本発明の目的は上記従来技術の問題点を改善し、。(Purpose of the invention) An object of the present invention is to improve the problems of the prior art described above.
高耐圧で高集積化が可能なＭＯＳトランジスタあるいは
Ｍ ＯＳキャパシタあるいは素子間分離領域を捉供する
ことにある。The object of the present invention is to provide a MOS transistor, a MOS capacitor, or an isolation region between elements, which can have a high breakdown voltage and be highly integrated.
本発明では上記目的を達成するために、半導体基板に診
けられた深孔のコーナー部分に形成された酸化膜の膜厚
を厚く、しかもなめらかな形状とし、あるいは２種類以
上の膜厚の酸化膜より成る段差部分の形状をなめらかな
ものとすることにより、該酸化膜のコーナー部分あるい
は段差部分への電界集中を抑え、高耐圧化を図ることを
特徴とする６
〔発明の実施例〕
以下、本発明の詳細な説明を実施例を用いて行なう。In order to achieve the above object, the present invention makes the oxide film formed at the corner part of the deep hole in the semiconductor substrate thick and has a smooth shape, or the oxide film has two or more different thicknesses. By making the shape of the step portion made of the film smooth, electric field concentration on the corner portion or step portion of the oxide film is suppressed, and a high withstand voltage is achieved.6 [Embodiments of the Invention] The following , a detailed explanation of the present invention will be given using examples.
第１図は段差部分での酸化膜を持つキャパシタの断面構
造図である。第１図（Ａ）は溝キャパシタに見られる。FIG. 1 is a cross-sectional structural diagram of a capacitor having an oxide film at a stepped portion. FIG. 1A shows a trench capacitor.
半導体基板１を選択的にエツチングし、しかる後熱酸化
により該半導体基板上に酸化膜２を形成し、さらに該酸
化膜上にゲート電極３を形成したキャパシタの断面構造
図である。第１図（Ｂ）は半導体基板１上に形成された
酸化膜２′が段差形状を有し、さらに該酸化膜上にゲー
ト電極３を形成したキャパシタの断面構造図である。1 is a cross-sectional structural diagram of a capacitor in which a semiconductor substrate 1 is selectively etched, an oxide film 2 is formed on the semiconductor substrate by thermal oxidation, and a gate electrode 3 is further formed on the oxide film. FIG. 1(B) is a cross-sectional structural view of a capacitor in which an oxide film 2' formed on a semiconductor substrate 1 has a stepped shape, and a gate electrode 3 is further formed on the oxide film.
これらの断面構造を有するキャパシタでは、従来の平坦
な断面構造を有するキャパシタに比べ、絶縁膜２，２′
の耐圧が低下する。In capacitors with these cross-sectional structures, the insulating films 2, 2'
pressure resistance decreases.
第２図（Ａ）は平坦な酸化膜を有するキャパシタの耐圧
（１０−”Ａ以上の電流が流れるときの印加電圧）を測
定し、ヒストグラムとして示したものである。平均耐圧
は１７Ｖ （８，５ＭＶ／ａ＋１）で落ちこぼれもない
が、第２図（Ｂ）に示した段差部分を持つ酸化膜を有す
るキャパシタの平均耐圧は１５Ｖ （７，５ＭＶ／ａｍ
）と低下し、落チコぼれも見られる。このような耐圧劣
化の原因は、酸化膜の段差部分に電界が集中するためと
考えられ、電界集中を緩和する構造を実現することによ
り耐圧劣化を抑えることができる。Figure 2 (A) shows a histogram of the withstand voltage (applied voltage when a current of 10-''A or more flows) of a capacitor with a flat oxide film.The average withstand voltage is 17V (8, 5MV/a+1), with no dropout, but the average withstand voltage of a capacitor with an oxide film with a stepped portion shown in Figure 2 (B) is 15V (7.5MV/am).
), and some declines can be seen. The cause of such breakdown voltage deterioration is thought to be that the electric field concentrates on the step portion of the oxide film, and by realizing a structure that alleviates the electric field concentration, breakdown voltage degradation can be suppressed.
第３図（Ａ）および（Ｂ）はそれぞれ半導体基板１およ
び酸化膜２′の段差部分のテーパーを設け、電界集中を
押えたキャパシタの実施例を示す断面構造である。これ
らの構造の酸化膜にかかる電界 □；の強さは
テーパーの角度θに大きく依存する。θが４５°より小
さいときに電界緩和の効果は太きく耐圧低下は少ない。FIGS. 3A and 3B are cross-sectional structures showing an embodiment of a capacitor in which the step portions of the semiconductor substrate 1 and the oxide film 2' are tapered to suppress electric field concentration. The strength of the electric field □; applied to the oxide film in these structures largely depends on the taper angle θ. When θ is smaller than 45°, the effect of electric field relaxation is large and the breakdown voltage drop is small.
第４図は第３図で設けたテーパー５を段差全体ではなく
、段差のコーナー部分にだけ設けて電界の緩和と微細加
工性を同時に満足させた実施例を示す断面図である。ま
たこれらの構造では、電界集中の原因の１つと考えられ
る段差部分での酸化膜厚減少を防ぐこともできる。FIG. 4 is a cross-sectional view showing an embodiment in which the taper 5 shown in FIG. 3 is provided not over the entire step but only at the corner portion of the step to simultaneously satisfy electric field relaxation and fine machinability. Furthermore, these structures can also prevent a decrease in the oxide film thickness at the step portion, which is considered to be one of the causes of electric field concentration.
第５図は半導体基板１に深孔６を形成した後、該深孔上
部７をテーパー状にエツチングし、その上に熱酸化膜２
を形成し１次にゲート電極３を形成したＭＯＳキャパシ
タの実施例を示す断面図である。本構造では深孔上部の
エツジ部分の酸化膜に集中する電界を緩和し、耐圧劣化
を低減することができる。FIG. 5 shows that after a deep hole 6 is formed in a semiconductor substrate 1, the upper part 7 of the deep hole is etched into a tapered shape, and a thermal oxide film 2 is placed on it.
FIG. 2 is a cross-sectional view showing an example of a MOS capacitor in which a gate electrode 3 is first formed. With this structure, the electric field concentrated on the oxide film at the edge portion above the deep hole can be relaxed, and breakdown voltage deterioration can be reduced.
次に、上記深孔上に形成された酸化膜において、該深孔
の底部での段差による酸化膜耐圧劣化を抑制する構造を
第６図に示し、ＣＶ Ｄ （Ｃｈｓｎ＋１ｃａｌＶａｐ
ｅｒ ［’ａｐｏｓｉｔｉｏｎ）法を用いたその製造方
法を第７図に示す。Next, in the oxide film formed on the deep hole, a structure for suppressing the deterioration of the oxide film breakdown voltage due to the step at the bottom of the deep hole is shown in FIG.
The manufacturing method using the er ['aposition) method is shown in FIG.
半導体基板１に形成された深孔６上に簿い酸化膜２を形
成した場合、その断面形状は第６図（Ａ）に示したよう
に、深孔底部のコーナーで膜厚が薄くなり、ここに電界
が集中し、耐圧が低下する。When a thin oxide film 2 is formed on a deep hole 6 formed in a semiconductor substrate 1, its cross-sectional shape is as shown in FIG. The electric field concentrates here and the withstand voltage decreases.
そこで、第６図（Ｂ）に示す様な形状の酸化膜２を形成
することにより、深孔底部コーナーでの酸化膜厚の減少
と段差形状の影響による電界集中を抑制することができ
る。Therefore, by forming the oxide film 2 having a shape as shown in FIG. 6(B), it is possible to suppress the reduction in the oxide film thickness at the bottom corner of the deep hole and the concentration of electric field due to the influence of the step shape.
以下に第６図（Ｂ）に示す構造を実現する製造方法を説
明する。まず、半導体基板１に深孔６を形成しく第７図
Ａ）、該深孔６を完全に埋めつくすように絶縁膜４をＣ
ＶＤ法を用いて形成する（第７図Ｂ）。次に該絶縁膜４
を上記深孔６の底部コーナーにのみ残存させるようにド
ライエツチングにより除去する（第７図Ｃ）、その後、
ＣＶＤ法により酸化膜２を形成する。この酸化膜は、深
孔底部の段差形状の影響による耐圧劣化を伴なわない良
質の絶縁膜として働く。さらに上記酸化膜２を用いてＭ
ＯＳキャパシタを構成する場合には。A manufacturing method for realizing the structure shown in FIG. 6(B) will be described below. First, a deep hole 6 is formed in the semiconductor substrate 1 (FIG. 7A), and the insulating film 4 is coated so as to completely fill the deep hole 6.
It is formed using the VD method (FIG. 7B). Next, the insulating film 4
is removed by dry etching so that it remains only at the bottom corner of the deep hole 6 (FIG. 7C), and then,
Oxide film 2 is formed by CVD method. This oxide film functions as a high-quality insulating film that does not cause deterioration in breakdown voltage due to the step shape at the bottom of the deep hole. Furthermore, using the oxide film 2, M
When configuring an OS capacitor.
ゲート電極３を形成する（第７図Ｄ）。A gate electrode 3 is formed (FIG. 7D).
第８図には深孔６の上部及び下部にテーパーをつけ、絶
縁膜２のコーナー部における耐圧低下を防止した実施例
を示す。FIG. 8 shows an embodiment in which the upper and lower parts of the deep hole 6 are tapered to prevent a drop in breakdown voltage at the corner portions of the insulating film 2.
本発明によれば、たとえば１ミクロン以下という微３■
なＭＯＳトランジスタあるいはＭＯＳキャパシタのｔ１
２化膜についても、ｒ９．差部での絶縁耐圧低下を抑え
ることができるので、イａ頼性が高くかつ高集積化が可
能なデバイスを提供することかできる。According to the present invention, for example, a micrometer of 1 micron or less
t1 of a MOS transistor or MOS capacitor
Regarding the bilayer film, r9. Since a drop in dielectric strength voltage at the differential portion can be suppressed, it is possible to provide a device that has high reliability and can be highly integrated.
なお１本発明は実施例に限定されることなく、ｒＦ９
本発明の思想を逸脱しない範囲で種々変ｌが可能である
。例えば、本発明による深孔内部の酸化膜は素そ分１１
領域の酸化膜であってもよい。Note that the present invention is not limited to the embodiments, and various changes can be made without departing from the spirit of the present invention. For example, the oxide film inside the deep hole according to the present invention is
It may also be an oxide film in the region.
第１図は段差部分での酸化膜を持つＭＯＳキャパシタの
断面構造図、第２図はＭＯＳキャパシタの耐圧を示すヒ
ストグラム、第３図乃至第８図は本発明の詳細な説明す
るための図である。
１・・・半導体基板、２，２′・・・酸化膜、３，３′
・・・ゲート電極、４・・・絶縁膜、５・・・コーナー
部、６・・・冨 １ 図
（Δう
ｆＪ ２ 口
（Ａン
司壊電μ （Ｖ）
ＣＢ）
１壊電β（１）
ｙＰＪ４ 図（ｂシ
ネ ５ 出
箒５図
第７図
（Ａ）
石 ７ 図
（ＣンFig. 1 is a cross-sectional structural diagram of a MOS capacitor having an oxide film at the stepped portion, Fig. 2 is a histogram showing the withstand voltage of the MOS capacitor, and Figs. 3 to 8 are diagrams for explaining the present invention in detail. be. 1... Semiconductor substrate, 2, 2'... Oxide film, 3, 3'
...Gate electrode, 4...Insulating film, 5...Corner part, 6...Fuji 1 Figure (ΔUfJ 2 mouth (Answer breakdown electric μ (V) CB) 1 breakdown electric charge β ( 1) yPJ4 figure (b cine 5 broom 5 figure 7 (A) stone 7 figure (C
Claims (1)
おいて、上記半導体基板表面を選択的にエッチングして
深孔を形成した後、上記深孔のコーナー部分あるいは、
上記酸化膜の段差部分にテーパーを有した形状の酸化膜
を形成したことを特徴とする半導体装置。In a semiconductor device in which a thin oxide film is formed on a semiconductor substrate, after selectively etching the surface of the semiconductor substrate to form a deep hole, a corner portion of the deep hole or
A semiconductor device characterized in that an oxide film having a tapered shape is formed in a stepped portion of the oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59227727A JPS61107756A (en) | 1984-10-31 | 1984-10-31 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59227727A JPS61107756A (en) | 1984-10-31 | 1984-10-31 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61107756A true JPS61107756A (en) | 1986-05-26 |
Family
ID=16865409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59227727A Pending JPS61107756A (en) | 1984-10-31 | 1984-10-31 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61107756A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01251736A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Manufacture of semiconductor device |
| JP2010206012A (en) * | 2009-03-04 | 2010-09-16 | Nissan Motor Co Ltd | Semiconductor device |
| JP2014241434A (en) * | 2014-08-06 | 2014-12-25 | 日産自動車株式会社 | Semiconductor device |
-
1984
- 1984-10-31 JP JP59227727A patent/JPS61107756A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01251736A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Manufacture of semiconductor device |
| JP2010206012A (en) * | 2009-03-04 | 2010-09-16 | Nissan Motor Co Ltd | Semiconductor device |
| JP2014241434A (en) * | 2014-08-06 | 2014-12-25 | 日産自動車株式会社 | Semiconductor device |
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