KR970023991A - Separation method of semiconductor device using Y-shaped trench - Google Patents

Separation method of semiconductor device using Y-shaped trench Download PDF

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KR970023991A
KR970023991A KR1019950036860A KR19950036860A KR970023991A KR 970023991 A KR970023991 A KR 970023991A KR 1019950036860 A KR1019950036860 A KR 1019950036860A KR 19950036860 A KR19950036860 A KR 19950036860A KR 970023991 A KR970023991 A KR 970023991A
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South Korea
Prior art keywords
trench
insulating material
etching
semiconductor substrate
layer
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KR1019950036860A
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Korean (ko)
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KR0165453B1 (en
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김성의
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Abstract

반도체 소자의 소자 분리 방법에 대해 기재되어 있다. 특수한 형상, 즉 Y자형의 트렌치를 형성하고 여기에 절연 물질을 채워 소자 분리막을 형성한다. 먼저 반도체 기판 위에 산화물층과 식각 방지를 위한 실리콘 질화물층을 순차적으로 형성한 후, 이 두 물질층을 선택적으로 식각하여 개구부를 형성한다. 이 개구부의 양 측벽에 식각 방지를 위한 실리콘 산화물의 스페이서를 형성한 후, 스페이서를 통해 노출된 반도체 기판을 등방성 식각을 행하고 연이어 이방성 식각을 행하여 Y자형 트렌치를 형성한다. 트렌치 측벽의 스페이서는 트렌치에 절연 물질을 채우기 전에 제거한다. 그 후 트렌치는 절연 물질로 채워진다. 절연 물질이 채워진 반도체 기판 표면은 화학기계적 연마 방식 등에 의해 소자 분리막 형성이 마무리된다. 이러한 반도체 소자의 분리 방법에 의하면 종래의 트렌치 형성 과정에서 발생하는 플라즈마 손상에 의한 트렌치의 필드에지에서의 결함을 방지할 수 있다. 또한, Y자형 트렌치는 절연물층진도를 증가시켜 트렌치에 매립된 절연 물질 사이에 보이드나 심이 발생하는 것을 방지하여 누설 전류를 방지할 수 있다. 결국, 반도체 소자의 분리를 위한 과정에서 유발되는 문제점을 해결하여 소자의 전기적 특성을 개선시킬 수 있는 반도체 소자의 분리 방법에 관한 것이다.A device isolation method for semiconductor devices is described. A special shape, that is, a Y-shaped trench is formed and an insulating material is filled therein to form an element isolation film. First, an oxide layer and a silicon nitride layer for etching prevention are sequentially formed on the semiconductor substrate, and then the two material layers are selectively etched to form openings. After forming spacers of silicon oxide for etching prevention on both sidewalls of the openings, the semiconductor substrate exposed through the spacers is subjected to isotropic etching and subsequently anisotropic etching to form a Y-shaped trench. Spacers in the trench sidewalls are removed before filling the trench with insulating material. The trench is then filled with insulating material. On the surface of the semiconductor substrate filled with the insulating material, the device isolation layer is finished by chemical mechanical polishing or the like. According to the semiconductor device separation method, a defect in the field edge of the trench due to plasma damage generated in the conventional trench formation process can be prevented. In addition, the Y-shaped trench may increase the insulation layer intensity to prevent the occurrence of voids or seams between the insulating material embedded in the trench to prevent leakage current. After all, the present invention relates to a method of separating a semiconductor device capable of improving electrical characteristics of the device by solving a problem caused in the process of separating the semiconductor device.

Description

Y자형 트렌치를 이용한 반도체 소자의 분리 방법Separation method of semiconductor device using Y-shaped trench

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 내지 제5도는 종래의 반도체 소자의 분리 방법인 수직형 트렌치를 이용한 소자 분리 과정을 순차적으로 설명하기 위해 도시한 단면도들이다,1 to 5 are cross-sectional views sequentially illustrating a device isolation process using a vertical trench, which is a conventional method of separating semiconductor devices.

제6도 내지 제13도는 본 발명에 의한 반도체 소자의 분리 방법을 순차적으로 설명하기 위하여 도시한 단면도들이다.6 to 13 are cross-sectional views sequentially illustrating a method of separating a semiconductor device according to the present invention.

Claims (4)

반도체 소자의 소자 분리 방법에 있어서, 반도체 기판 위에 제1산화물층과 식각 방지를 위한 제1물질층을 순차적으로 형성하는 제1단계; 상기 제1산화물층과 제1물질층을 선택적으로 식각함으로써 비활성 영역의 반도체 기판이 노출되는 개구부를 형성하는 제2단계; 상기 개구부의 양 측벽에 식각 방지를 위한 제2물질의 스페이서를 형성하는 제3단계; 상기의 스페이서를 통해 노출된 반도체 기판을 등방성 식각을 행하여 접시 모양의 홈을 형성하는 제4단계; 상기의 제1물질층과 스페이서를 마스크로 하여 노출된 반도체 기판을 이방성 식각함으로써 Y자형 트렌치를 형성하는 제5단계; 상기의 스페이서를 제거하는 제6단계; 상기의 Y자헝 트렌치를 절연물질층으로 매립하는 제7단계; 및 상기의 제1물질층이 드러날 때까지 절연물질층을 에치백(Etch back)하여 Y자형 소자 분리막을 형성하는 제8단계를 포함하는 것을 특징으로 하는 반도체 소자의 분리 방법.A device isolation method for a semiconductor device, comprising: a first step of sequentially forming a first oxide layer and a first material layer for etching prevention on a semiconductor substrate; Selectively etching the first oxide layer and the first material layer to form an opening through which the semiconductor substrate in the inactive region is exposed; Forming a spacer of a second material to prevent etching on both sidewalls of the opening; A fourth step of isotropically etching the semiconductor substrate exposed through the spacers to form a dish-shaped groove; Forming a Y-shaped trench by anisotropically etching the exposed semiconductor substrate using the first material layer and the spacer as a mask; A sixth step of removing the spacer; A seventh step of filling the Y-shaped trench with an insulating material layer; And an eighth step of etching back the insulating material layer until the first material layer is exposed to form a Y-type device isolation layer. 제1항에 있어서, 상기 제1물질층은 실리콘 질화물을 사용하여 형성되는 것을 특징으로 하는 반도체 소자의 분리 방법.The method of claim 1, wherein the first material layer is formed using silicon nitride. 제1항에 있어서, 상기 제2물질은 실리콘 산화물을 사용하여 형성되는 것을 특징으로 하는 반도체 소자의 분리 방법.The method of claim 1, wherein the second material is formed using silicon oxide. 제1항에 있어서, 상기 에치백(Etch back)은 화학 기계적 연마방식(Chemical-Mechanical Polishing)으로 행하는 것을 특징으로 하는 반도체 소자의 분리 방법.The method of claim 1, wherein the etch back is performed by chemical-mechanical polishing. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950036860A 1995-10-24 1995-10-24 Method of isolation on a semiconductor device KR0165453B1 (en)

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KR0165453B1 KR0165453B1 (en) 1999-02-01

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100299379B1 (en) * 1998-06-30 2002-10-25 주식회사 하이닉스반도체 Method for forming metal wiring in semiconductor device
KR100456530B1 (en) * 2001-12-27 2004-11-10 동부전자 주식회사 Shallow trench isolation forming method of semiconductor device
KR100470161B1 (en) * 1998-06-29 2005-04-06 주식회사 하이닉스반도체 Method of manufacturing semiconductor device isolation film using trench

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100702775B1 (en) 2005-05-03 2007-04-03 주식회사 하이닉스반도체 Method for forming isolation in semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100470161B1 (en) * 1998-06-29 2005-04-06 주식회사 하이닉스반도체 Method of manufacturing semiconductor device isolation film using trench
KR100299379B1 (en) * 1998-06-30 2002-10-25 주식회사 하이닉스반도체 Method for forming metal wiring in semiconductor device
KR100456530B1 (en) * 2001-12-27 2004-11-10 동부전자 주식회사 Shallow trench isolation forming method of semiconductor device

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