KR0147487B1 - Method for forming insulation film of semiconductor device - Google Patents

Method for forming insulation film of semiconductor device

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Publication number
KR0147487B1
KR0147487B1 KR1019950006705A KR19950006705A KR0147487B1 KR 0147487 B1 KR0147487 B1 KR 0147487B1 KR 1019950006705 A KR1019950006705 A KR 1019950006705A KR 19950006705 A KR19950006705 A KR 19950006705A KR 0147487 B1 KR0147487 B1 KR 0147487B1
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KR
South Korea
Prior art keywords
film
forming
trench
semiconductor substrate
device isolation
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KR1019950006705A
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Korean (ko)
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KR960035962A (en
Inventor
박상훈
Original Assignee
김주용
현대전자산업주식회사
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Priority to KR1019950006705A priority Critical patent/KR0147487B1/en
Publication of KR960035962A publication Critical patent/KR960035962A/en
Application granted granted Critical
Publication of KR0147487B1 publication Critical patent/KR0147487B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Abstract

본 발명은 반도체 기판의 예정된 소자분리영역에 트렌치를 형성하는 제1단계; 반도체 기판 상부 표면을 따라 일정두께로 TaXOY막을 형성하는 제2단계; 전체구조 상부에 절연막을 형성하여 트렌치를 완전히 매립하는 제3단계; 트렌치 내부 이외의 반도체 기판 표면이 노출될때까지 평탄화 식각하는 제4단계; 및 열적산화 공정으로 제1산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 소자분리막 형성방법에 관한 것으로, Ta2O5막을 채용한 소자분리막 형성으로 절연효과가 향상되어 소자의 특성 향상 및 수율향상을 가져오는 효과가 있다.A first step of forming a trench in a predetermined device isolation region of a semiconductor substrate; Forming a Ta X O Y film along a top surface of the semiconductor substrate at a predetermined thickness; Forming a dielectric film over the entire structure to completely fill the trench; A fourth step of planarization etching until the surface of the semiconductor substrate other than the inside of the trench is exposed; And forming a first oxide film by a thermal oxidation process, wherein the isolation effect is improved by forming a device isolation film employing a Ta 2 O 5 film, thereby improving device characteristics and improving yield. Has the effect of bringing.

Description

소자분리막 형성방법Device Separator Formation Method

제1도는 종래기술에 따라 형성된 소자분리막 단면도.1 is a cross-sectional view of an isolation layer formed in accordance with the prior art.

제2a도 내지 제2d도는 본 발명의 일실시예에 따른 소자분리막 형성 공정도.2a to 2d is a device isolation film forming process according to an embodiment of the present invention.

제3a도 및 제3b도는 본 발명의 다른 실시예에 따른 소자분리막 형성 공정도.3A and 3B illustrate a process of forming a device isolation film according to another exemplary embodiment of the present invention.

제4a도 내지 제4c도는 본 발명의 또다른 실시예에 따른 소자분리막 형성 공정도.4A through 4C are diagrams illustrating a device isolation film forming process according to still another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

211 : 실리콘 기판 212 : 감광막 패턴211 silicon substrate 212 photoresist pattern

213 : 트렌치 영역 214 : 열산화막213 trench region 214 thermal oxide film

25 : Ta2O5막 216 : SOG막25: Ta 2 O 5 film 216: SOG film

217 : TEOS 산화막 218 : 캡 산화막217 TEOS oxide film 218 Cap oxide film

219 : 폴리실리콘막219 polysilicon film

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 특히 트렌치 형태의 소자분리막을 Ta2O5, SOG막(spin-on-glass막), TEOS산화막을 사용하여 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a trench isolation device separation film using a Ta 2 O 5 , a spin-on-glass film, and a TEOS oxide film.

제1도를 통해 종래의 소자분리막 형성방법을 살펴보면, 실리콘기판(1)을 소정두께 식각하여 트렌치를 형성하고, 얇은 질화막(2)을 전체구조 상부에 형성한 후, TEOS 산화막(3)으로 트렌치를 매립하여 소자분리막을 형성하였다.Referring to the conventional method of forming a device isolation film through FIG. 1, a trench is formed by etching a silicon substrate 1 to a predetermined thickness, a thin nitride film 2 is formed on the entire structure, and then a trench is formed using a TEOS oxide film 3. Was embedded to form an isolation layer.

그러나, 상기와 같은 종래의 소자분리막 형성 방법은 질화막과 TEOS산화막간의 스트레스가 작용하여 이후의 열공정시에 절연특성이 악화되는 문제점이 있었다.However, the conventional method of forming a device isolation film as described above has a problem in that the stress between the nitride film and the TEOS oxide film acts, resulting in deterioration of the insulating properties during the subsequent thermal process.

상기 종래 문제점을 해결하기 위하여 안출된 본 발명은 절연특성이 향상되어 소자의 특성을 향상시키는 반도체 소자의 소자분리막 형성방법을 제공함을 그 목적으로 한다.An object of the present invention is to provide a method for forming a device isolation film of a semiconductor device to improve the characteristics of the device is improved the insulating properties to solve the conventional problems.

상기 목적을 달성하기 위하여 본 발명은 반도체 기판의 예정된 소자분리영역에 트렌치를 형성하는 제1단계; 반도체 기판 상부 표면을 따라 일정두께로 TaXOY막을 형성하는 제2단계; 전체구조 상부에 절연막을 형성하여 트렌치를 완전히 매립하는 제3단계; 트렌치 내부 이외의 반도체 기판 표면이 노출될때까지 평탄화 식각하는 제4단계; 및 열적산화 공정으로 제1산화막을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention provides a first step of forming a trench in a predetermined device isolation region of a semiconductor substrate to achieve the above object; Forming a Ta X O Y film along a top surface of the semiconductor substrate at a predetermined thickness; Forming a dielectric film over the entire structure to completely fill the trench; A fourth step of planarization etching until the surface of the semiconductor substrate other than the inside of the trench is exposed; And forming a first oxide film by a thermal oxidation process.

이하, 첨부된 도면 제2a도 내지 제4c도를 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the attached drawings 2A to 4C.

제2a도 내지 제2d도는 본 발명의 일실시예에 따른 소자분리막 형성 고정도로서, 먼저, 제2a도와 같이 실리콘 기판(211)상에 감광막 패턴(212)을 형성하고 비등방성 식각법으로 실리콘기판(211)내에 트렌치 영역(213)을 형성한 다음, 채널 스토퍼용 BF2분자를 20~70Kev, 1×1011~1×1017원자/cm2의 조건으로 이온주입한다. 이때 트렌치 깊이는 0.5~1.2㎛ 정도로 형성한다.2A to 2D are high accuracy of device isolation film formation according to an embodiment of the present invention. First, as shown in FIG. 2A, the photosensitive film pattern 212 is formed on the silicon substrate 211, and the silicon substrate is formed by anisotropic etching. After the trench region 213 is formed in 211), the BF 2 molecules for the channel stopper are ion implanted under the conditions of 20 to 70 Kev and 1 x 10 11 to 1 x 10 17 atoms / cm 2 . At this time, the trench depth is formed about 0.5 ~ 1.2㎛.

이어서, 제2b도와 같이 상기 감광막 패턴(212)을 제거한 다음에, 약 100~300Å의 열산화막(214)을 형성하고, Ta(OCH2CH3)5인 탄탈륨 에사옥사이드(Tantalum ethoxide) 및 O2가스를 사용한 400~500℃의 온도범위에서 100~200Å 두께로 Ta2O5막(215)을 형성하고, UV-03 및 건식 O2에 의한 열처리를 실시한다.Subsequently, after removing the photosensitive film pattern 212 as shown in FIG. 2B, a thermal oxide film 214 having a thickness of about 100 to 300 kPa is formed, and tantalum ethoxide and O 2 of Ta (OCH 2 CH 3 ) 5 are formed. A Ta 2 O 5 film 215 is formed to a thickness of 100 to 200 Pa in a temperature range of 400 to 500 ° C. using gas, and heat treatment is performed by UV-03 and dry O 2 .

이때, 상기 열산화막(214)은 실리콘 기판(211)과 Ta 원자간의 반응을 억제하기 위한 완충목적으로 형성한다.At this time, the thermal oxide film 214 is formed as a buffer for suppressing the reaction between the silicon substrate 211 and Ta atoms.

이어서, 제2c도와 같이 3000~6000Å의 SOG막(216)을 도포하여 트렌치 영역(213)을 1차 매립한 다음, TEOS 산화막(217)을 4000~6000Å 정도로 증착하여 2차 매립한다.Next, as shown in FIG. 2C, the trench region 213 is first filled by applying the SOG film 216 of 3000 to 6000 mV, and then the TEOS oxide film 217 is deposited to about 4000 to 6000 mV, and the second landfill is deposited.

끝으로, 제2d도는 화학적 기계적 폴리싱(polishing)방법으로 실리콘 기판(211)을 노출시킨 다음에, SOG막(216)의 노출을 방지하기 위해 캡 산화막(218)을 약 100~200Å 정도로 형성한다.Finally, in FIG. 2D, after exposing the silicon substrate 211 by a chemical mechanical polishing method, a cap oxide film 218 is formed at about 100 to about 200 kPa to prevent the SOG film 216 from being exposed.

제3a도 및 제3b도는 본 발명의 다른 실시예에 따른 소자분리막 형성 공정도로서, 제3a도는 상기 제2a도 내지 제2c도까지 공정을 진행한후, 제2c도의 상태에서 CF4, CHF3가스를 사용한 전면식각으로 실리콘 기판(211)을 노출시킨 것으로, 이때 TEOS 산화막(217)에 소정의 요홈부위가 발생한다.3a and 3b are diagrams illustrating a process of forming a device isolation film according to another embodiment of the present invention, and FIG. 3a is a CF 4 , CHF 3 gas in a state of FIG. 2c after the processes of FIGS. 2a to 2c are performed. The silicon substrate 211 is exposed by the front surface etching using a predetermined recess, and a predetermined recess portion is generated in the TEOS oxide film 217.

이어서, 제3b도는 500~1000Å의 폴리실리콘막(219)을 증착 및 비등방성 전면식각하여 요홈부위를 매립하고, 100~300Å의 열산화막(218)을 형성하여 폴리실리콘막(219)을 산화시키면서 노출된 SOG막(216)을 보호한다.Subsequently, in FIG. 3B, the grooves are filled by depositing and anisotropically etching the polysilicon film 219 of 500 to 1000 GPa, and the thermal oxide film 218 of 100 to 300 GPi is formed to oxidize the polysilicon film 219. The exposed SOG film 216 is protected.

제4a도 내지 제4c도는 본 발명의 또다른 실시예에 따른 소자 분리막 형성 공정도로서, 제4a도는 상기 제2a도 및 2b도까지 공정을 진행한후, 제2b도의 상태에서 전체구조 상부에 TEOS 산화막(217)을 8000~10000Å 정도로 증착한 상태이다.4A to 4C are diagrams illustrating a process of forming a device isolation layer according to still another embodiment of the present invention. FIG. 4A is a process of forming the TEOS oxide film on the entire structure in the state of FIG. (217) is in a state of being deposited at about 8000 to 10000 Pa.

이어서, 제4b도는 CF4, CHF3가스를 사용한 전면식각으로 실리콘 기판(211)을 노출시킨 것으로, 이때 역시 TEOS 산화막(217)에 소정의 요홈부위가 발생한다.Subsequently, in FIG. 4B, the silicon substrate 211 is exposed by full etching using CF 4 and CHF 3 gas, and at this time, a predetermined recess is generated in the TEOS oxide film 217.

끝으로, 제4c도는 500~1000Å의 폴리실리콘막(219)을 증착 및 비등방성 전면식각하여 요홈부위를 매립하고, 200~500Å의 열산화막(218)을 형성하는데, 이때 폴리실리콘막(219)은 산화된다.Finally, FIG. 4C shows that the polysilicon film 219 of 500 to 1000 kV is deposited and anisotropically etched to bury the recessed portion, and the thermal oxide film 218 of 200 to 500 kPa is formed, wherein the polysilicon film 219 is formed. Is oxidized.

이상, 상기 설명과 같은 본 발명은 Ta2O5막을 채용한 소자분리막 형성으로 절연효과가 향상되어 소자의 특성 및 제조 수율을 향상시키는 효과가 있다.As described above, the present invention as described above has the effect of improving the insulation effect by forming a device isolation film employing a Ta 2 O 5 film to improve the characteristics and manufacturing yield of the device.

Claims (8)

반도체 기판의 예정된 소자분리영역에 트렌치를 형성하는 제1단계; 반도체 기판 상부 표면을 따라 일정두께로 TaXOY막을 형성하는 제2단계; 전체구조 상부에 절연막을 형성하여 트렌치를 완전히 매립하는 제3단계; 트렌치 내부 이외의 반도체 기판 표면이 노출될때까지 평탄화 식각하는 제4단계; 및 열적산화 공정으로 제1산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 소자분리막 형성방법.Forming a trench in a predetermined device isolation region of the semiconductor substrate; Forming a Ta X O Y film along a top surface of the semiconductor substrate at a predetermined thickness; Forming a dielectric film over the entire structure to completely fill the trench; A fourth step of planarization etching until the surface of the semiconductor substrate other than the inside of the trench is exposed; And forming a first oxide film by a thermal oxidation process. 제1항에 있어서; 상기 제1단계 및 제2단계 사이에 실시하여, 상기 반도체 기판 표면 및 TaXOY막 계면에 얇은 제2산화막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 1; And forming a thin second oxide film between the surface of the semiconductor substrate and the Ta X O Y film interface between the first step and the second step. 제1항에 있어서; 상기 TaXOY막은 400~500℃의 온도범위에서 Ta(OCH2CH3)5인 탄탈륨에사옥사이드 및 O2가스를 사용하여 형성되는 Ta2O5막인 것을 특징으로 하는 소자분리막 형성방법.The method of claim 1; The Ta X O Y film is a Ta 2 O 5 film formed using a Ta (OCH 2 CH 3 ) 5 tantalum ethane oxide and O 2 gas in a temperature range of 400 ~ 500 ℃. 제1항에 있어서; 상기 절연막은 SOG막과 TEOS산화막이 차례로 적층된 구조의 절연막인 것을 특징으로 하는 소자분리막 형성방법.The method of claim 1; And the insulating film is an insulating film having a structure in which an SOG film and a TEOS oxide film are sequentially stacked. 제1항에 있어서, 상기 절연막은 TEOS 산화막인 것을 특징으로 하는 소자분리막 형성방법.The method of claim 1, wherein the insulating film is a TEOS oxide film. 제4항에 있어서; 상기 제4단계는 화학적 기계적 폴리싱(polishing)방법으로 이루어지는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 4; The fourth step is a device isolation film forming method, characterized in that the chemical mechanical polishing (polishing) method. 제4항 또는 제5항에 있어서; 상기 제4단계는 CF4, CHF3가스를 사용한 전면식각으로 이루어지는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 4 or 5; The fourth step is a method of forming a device isolation film, characterized in that the front etching using a CF 4 , CHF 3 gas. 제7항에 있어서; 상기 CF4, CHF3가스를 사용한 전면식각 이후에 발생하는 요홈부위에 폴리실리콘막을 매립하는 단계를 더 포함하는 것을 특징으로 하는 소자분리막 형성방법.The method of claim 7; And embedding a polysilicon film in the recess portion generated after the front surface etching using the CF 4 and CHF 3 gas.
KR1019950006705A 1995-03-28 1995-03-28 Method for forming insulation film of semiconductor device KR0147487B1 (en)

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Publication number Priority date Publication date Assignee Title
KR100478496B1 (en) * 2002-12-05 2005-03-29 동부아남반도체 주식회사 Formation method of trench oxide in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100478496B1 (en) * 2002-12-05 2005-03-29 동부아남반도체 주식회사 Formation method of trench oxide in semiconductor device

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