KR100412137B1 - Method for forming gate spacer of semiconductor device - Google Patents
Method for forming gate spacer of semiconductor device Download PDFInfo
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- KR100412137B1 KR100412137B1 KR10-2001-0078071A KR20010078071A KR100412137B1 KR 100412137 B1 KR100412137 B1 KR 100412137B1 KR 20010078071 A KR20010078071 A KR 20010078071A KR 100412137 B1 KR100412137 B1 KR 100412137B1
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000005530 etching Methods 0.000 claims abstract description 25
- 150000004767 nitrides Chemical class 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 230000009969 flowable effect Effects 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract 2
- 239000012530 fluid Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 92
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- -1 nitride nitride Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 버퍼산화막을 갖는 질화막 재질의 게이트 스페이서의 형성 후에 상기 버퍼산화막이 식각되는 현상을 방지하기 위한 게이트 스페이서 형성방법을 개시하며, 개시된 본 발명의 방법은, 실리콘 기판 상에 게이트산화막, 게이트도전막 및 하드마스크막의 적층으로된 게이트 전극을 형성하는 단계; 상기 게이트 전극을 덮도록 기판 상에 버퍼산화막을 증착하는 단계; 상기 버퍼산화막 상에 상기 버퍼산화막 보다 상대적으로 빠른 식각 속도를 갖는 유동성 절연막을 소정 두께로 도포하는 단계; 상기 유동성 절연막과 버퍼산화막을 식각하여 상기 유동성 절연막을 제거함과 동시에 상기 하드마스크막의 표면에 형성된 버퍼산화막 부분을 제거하는 단계; 상기 단계까지의 결과물 상에 질화막을 증착하는 단계; 및 상기 게이트 전극의 측벽에 스페이서가 형성되도록 상기 질화막을 블랭킷 식각하는 단계를 포함하는 것을 특징으로 한다. 여기서, 상기 유동성 절연막은 SOG막, 또는, PSG막, BPSG막 및 O3-TEOS막 중에서 선택되는 어느 하나가 이용되며, 상기 버퍼산화막과의 식각선택비를 조절하기 위해 600∼900℃의 온도로 열처리된다.The present invention discloses a method of forming a gate spacer for preventing the buffer oxide film from being etched after the formation of a gate spacer of a nitride film material having a buffer oxide film. The disclosed method includes a gate oxide film and a gate conductive film on a silicon substrate. Forming a gate electrode formed of a stack of a film and a hard mask film; Depositing a buffer oxide film on a substrate to cover the gate electrode; Applying a flowable insulating film having a predetermined thickness on the buffer oxide film to have a relatively faster etching speed than the buffer oxide film; Etching the flow insulating film and the buffer oxide film to remove the flow insulating film and simultaneously removing a portion of the buffer oxide film formed on a surface of the hard mask film; Depositing a nitride film on the product up to the step; And blanket etching the nitride film to form a spacer on sidewalls of the gate electrode. Here, the flowable insulating film is any one selected from SOG film, PSG film, BPSG film and O 3 -TEOS film, and at a temperature of 600 ~ 900 ℃ to control the etching selectivity with the buffer oxide film Heat treatment.
Description
본 발명은 반도체 소자의 게이트 스페이서 형성방법에 관한 것으로, 특히, 버퍼산화막의 식각에 기인하는 전기적 쇼트의 발생을 방지할 수 있는 반도체 소자의 게이트 스페이서 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate spacer of a semiconductor device, and more particularly, to a method of forming a gate spacer of a semiconductor device capable of preventing generation of electrical shorts due to etching of a buffer oxide film.
주지된 바와 같이, 게이트 스페이서는 단채널효과를 방지하기 위한 하나의 방법인 LDD(Lightly Doped Drain)의 형성을 위해 형성하게 되었다.As is well known, gate spacers have been formed for the formation of Lightly Doped Drain (LDD), which is one method for preventing short channel effects.
그런데, 반도체 소자의 고집적화의 요구에 따라 다양한 공정 기술들이 개발되면서, 상기 게이트 스페이서는, 단지 LDD 영역을 형성하기 위한 기능 이외에, 인접하는 게이트 전극들간의 전기적 차단 수단으로서의 기능을 행하게 되었다.However, as various process technologies have been developed in accordance with the demand for high integration of semiconductor devices, the gate spacers, as well as a function for forming LDD regions, have a function as an electrical blocking means between adjacent gate electrodes.
예컨데, 상기 게이트 스페이서는 자기정렬콘택(Self-Aligned Contact) 공정이 적용되는 고집적 반도체 소자의 제조 공정에서 LDD 영역의 형성 수단으로서 보다는 인접하는 게이트 전극들간이 전기적 차단 수단으로서의 기능에 더 큰 의미가 부여되고 있는 실정이다.For example, the gate spacer has a greater meaning to function as an electrical blocking means between adjacent gate electrodes than as a means for forming an LDD region in a manufacturing process of a highly integrated semiconductor device to which a self-aligned contact process is applied. It's happening.
이와 같은 게이트 스페이서를 형성하기 위해, 종래에는 스페이서 물질로서 질화막을 사용하고 있으며, 그리고, 게이트 전극이 형성된 실리콘 기판 상에 질화막을 증착한 후, 이를 블랭킷(blanket) 식각한다.In order to form such a gate spacer, a nitride film is conventionally used as a spacer material, and after the nitride film is deposited on a silicon substrate on which the gate electrode is formed, a blanket is etched.
한편, 상기 질화막 재질의 스페이서는 전기적 절연 측면에서는 우수하지만, 그 형성 과정에서 질화막의 스트레스(stress)가 제품의 특성을 열화시키게 되는 단점을 갖고 있다.On the other hand, the spacer of the nitride film material is excellent in terms of electrical insulation, but has a disadvantage that the stress of the nitride film during the formation of the deterioration of the characteristics of the product.
따라서, 질화막의 스트레스에 의한 제품 특성의 열화를 방지하기 위해, 종래의 스페이서 형성 공정에서는 질화막의 증착 이전에 버퍼(buffer)막, 예컨데, 산화막을 증착하여 게이트와 질화막 스페이서 사이에 버퍼산화막이 개재되도록 하고 있다.Therefore, in order to prevent degradation of product characteristics due to stress of the nitride film, in the conventional spacer forming process, a buffer film, for example, an oxide film is deposited before the nitride film is deposited so that the buffer oxide film is interposed between the gate and the nitride spacer. Doing.
그러나, 전술한 구조의 게이트 스페이서는 그 자체로는 커다란 문제점이 없지만, 도 1에 도시된 바와 같이, 후속하는 콘택 공정에서 버퍼산화막(7)이 쉽게 식각되는 취약점이 있어서, 후속 공정이 진행됨에 따라 전기적 쇼트(short)와 같은 결함이 발생될 수 있고, 이로 인해, 소자 특성이 저하됨은 물론 제조수율이 저하되는 문제점이 있다.However, the gate spacer of the above-described structure does not have a big problem in itself, but as shown in FIG. 1, there is a vulnerability in that the buffer oxide film 7 is easily etched in a subsequent contact process. As a subsequent process proceeds, Defects such as electrical shorts may occur, and as a result, device characteristics may deteriorate and manufacturing yields may deteriorate.
도 1에서, 도면부호 1은 실리콘 기판, 2는 게이트 산화막, 3은 게이트 도전막, 4는 하드마스크막, 5는 게이트 전극, 6은 박막의 산화막, 7은 버퍼산화막, 그리고, 8은 질화막 재질의 게이트 스페이서를 각각 나타낸다.In Fig. 1, reference numeral 1 is a silicon substrate, 2 is a gate oxide film, 3 is a gate conductive film, 4 is a hard mask film, 5 is a gate electrode, 6 is a thin film oxide film, 7 is a buffer oxide film, and 8 is a nitride film material. Each gate spacer is shown.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 버퍼산화막을 갖는 구조로 질화막 재질의 스페이서를 형성하되, 후속하는 콘택 공정에서 상기 버퍼산화막의 원치않는 식각을 방지할 수 있는 반도체 소자의 게이트 스페이서 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made in order to solve the above problems, while forming a spacer of the nitride film material having a structure having a buffer oxide film, a semiconductor device capable of preventing unwanted etching of the buffer oxide film in a subsequent contact process It is an object of the present invention to provide a method for forming a gate spacer.
또한, 본 발명은 버퍼산화막의 원치않는 식각을 방지하여 소자 특성이 저하되는 것을 방지할 수 있는 반도체 소자의 게이트 스페이서 형성방법을 제공함에 그 다른 목적이 있다.Another object of the present invention is to provide a method of forming a gate spacer of a semiconductor device capable of preventing unwanted etching of a buffer oxide layer and thus preventing deterioration of device characteristics.
도 1은 종래 기술에 따라 형성된 버퍼산화막을 갖는 질화막 재질이 게이트 스페이서에서의 문제점을 설명하기 위한 도면.1 is a view illustrating a problem in a gate spacer of a nitride film material having a buffer oxide film formed according to the prior art.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 게이트 스페이서 형성방법을 설명하기 위한 공정별 단면도.2A through 2D are cross-sectional views illustrating processes for forming a gate spacer according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11 : 기판 12 : 게이트산화막11 substrate 12 gate oxide film
13 : 게이트도전막 14 : 하드마스크막13: gate conductive film 14: hard mask film
15 : 게이트 전극 16 : 박막의 산화막15 gate electrode 16 thin film oxide film
17 : 버퍼산화막 18 : SOG막17 buffer oxide film 18 SOG film
19 : 게이트 스페이서19: gate spacer
상기와 같은 목적을 달성하기 위한 본 발명의 게이트 스페이서 형성방법은, 실리콘 기판 상에 게이트산화막, 게이트도전막 및 하드마스크막의 적층으로된 게이트 전극을 형성하는 단계; 상기 게이트 전극을 덮도록 기판 상에 버퍼산화막을 증착하는 단계; 상기 버퍼산화막 상에 상기 버퍼산화막 보다 상대적으로 빠른 식각 속도를 갖는 유동성 절연막을 소정 두께로 도포하는 단계; 상기 유동성 절연막과 버퍼산화막을 식각하여 상기 유동성 절연막을 제거함과 동시에 상기 하드마스크막의 표면에 형성된 버퍼산화막 부분을 제거하는 단계; 상기 단계까지의 결과물 상에 질화막을 증착하는 단계; 및 상기 게이트 전극의 측벽에 스페이서가 형성되도록 상기 질화막을 블랭킷 식각하는 단계를 포함한다.The gate spacer forming method of the present invention for achieving the above object comprises the steps of forming a gate electrode of a stack of a gate oxide film, a gate conductive film and a hard mask film on a silicon substrate; Depositing a buffer oxide film on a substrate to cover the gate electrode; Applying a flowable insulating film having a predetermined thickness on the buffer oxide film to have a relatively faster etching speed than the buffer oxide film; Etching the flow insulating film and the buffer oxide film to remove the flow insulating film and simultaneously removing a portion of the buffer oxide film formed on a surface of the hard mask film; Depositing a nitride film on the product up to the step; And blanket etching the nitride film to form a spacer on sidewalls of the gate electrode.
여기서, 상기 유동성 절연막은 SOG막이며, PSG막, BPSG막 또는 O3-TEOS막도 이용 가능하다. 또한, 상기 유동성 절연막은 상기 버퍼산화막과의 식각선택비를 조절하기 위해 600∼900℃의 온도로 열처리된다. 게다가, 상기 유동성 절연막과 버퍼산화막의 식각은 HF 또는 BOE 용액을 이용한 습식 식각으로 수행한다.Here, the fluid insulating film is an SOG film, and a PSG film, a BPSG film, or an O 3 -TEOS film can also be used. In addition, the flow insulating film is heat-treated at a temperature of 600 ~ 900 ℃ to control the etching selectivity with the buffer oxide film. In addition, the etching of the flowable insulating film and the buffer oxide film is performed by wet etching using HF or BOE solution.
본 발명에 따르면, 버퍼산화막이 스페이서의 외부로 노출되지 않음으로써, 후속하는 콘택 공정에서 원치않는 식각이 방지되며, 그래서, 제조수율의 저하 및 신뢰성의 저하가 방지된다.According to the present invention, since the buffer oxide film is not exposed to the outside of the spacer, unwanted etching is prevented in a subsequent contact process, so that a decrease in manufacturing yield and a decrease in reliability are prevented.
(실시예)(Example)
이하, 첨부된 도면을 참조해서 본 발명의 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 게이트 스페이서 형성방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.2A through 2D are cross-sectional views illustrating processes for forming a gate spacer according to an exemplary embodiment of the present invention.
도 2a를 참조하면, 실리콘 기판(11) 상에 공지의 공정에 따라서 게이트산화막(12), 게이트도전막 및 하드마스크막(14)의 적층으로 이루어진 게이트 전극(15)을 형성한다. 그런다음, 상기 게이트 전극(15) 형성시에 발생되는 식각데미지를 회복시키고, 그리고, 후속하는 이온주입 공정에서 기판 손상을 방지하기 위해 열공정을 수행한다. 이때, 상기 열공정의 결과로, 기판(11) 표면과 게이트산화막(12) 및 게이트도전막(13)의 표면 상에는 박막의 산화막(6)이 형성된다.Referring to FIG. 2A, a gate electrode 15 formed of a stack of a gate oxide film 12, a gate conductive film and a hard mask film 14 is formed on a silicon substrate 11 according to a known process. Then, the etching damage generated when the gate electrode 15 is formed is recovered, and a thermal process is performed to prevent substrate damage in a subsequent ion implantation process. At this time, as a result of the thermal process, a thin film oxide film 6 is formed on the surface of the substrate 11, the gate oxide film 12, and the gate conductive film 13.
도 2b를 참조하면, 박막의 산화막(16)을 포함한 게이트 전극(15)을 덮도록 상기 기판 결과물 상에 버퍼산화막(17)을 증착한다. 그런다음, 버퍼산화막(17) 상에 특정 용액, 예컨데, HF 또는 BOE 용액에 대해 상기 버퍼산화막(17)과 상이한 식각 선택비를 갖는 유동성 산화막, 예컨데, SOG막(18)을 3,000∼4,000Å 두께로 도포한다.Referring to FIG. 2B, a buffer oxide layer 17 is deposited on the substrate resultant to cover the gate electrode 15 including the thin layer oxide layer 16. Then, the oxidized oxide film, eg, the SOG film 18, having a etch selectivity different from that of the buffer oxide film 17 for a specific solution, for example, an HF or BOE solution, on the buffer oxide film 17 is 3,000 to 4,000 Å thick. Apply with
도 2c를 참조하면, SOG막과 버퍼산화막을 그들간의 식각 속도(etch rate) 차이를 이용하여 HF 또는 BOE 용액으로 식각한다. 여기서, 상기 SOG막의 식각속도는 열공정(Thermal Annealing)에 의해 조절 가능하며, 본 발명의 실시예에서는 600∼900℃로 열공정을 수행한다. 상기 습식 식각의 결과, HF 또는 BOE 용액에 대해 상기 SOG막의 식각속도가 버퍼산화막의 그것 보다 빠른 것으로 인해, 도시된 바와 같이, 상기 SOG막은 대부분 제거되며, 그리고, 버퍼산화막(17)은 하드마스크막(14)의 상면과 측면에 형성된 일부가 제거된다.Referring to FIG. 2C, the SOG film and the buffer oxide film are etched with HF or BOE solution using the difference in etching rates between them. Here, the etching rate of the SOG film can be adjusted by a thermal process (Thermal Annealing), in the embodiment of the present invention is carried out the thermal process at 600 ~ 900 ℃. As a result of the wet etching, as the etching rate of the SOG film for the HF or BOE solution is faster than that of the buffer oxide film, as shown, the SOG film is mostly removed, and the buffer oxide film 17 is a hard mask film. A part formed in the upper surface and the side surface of 14 is removed.
도 2d를 참조하면, 상기 결과물 상에 스페이서용 질화막을 증착하고, 이를 블랭킷 식각하여 상기 게이트의 측벽에 버퍼산화막(18)이 개재된 질화막 재질의 게이트 스페이서(19)를 형성한다.Referring to FIG. 2D, a nitride nitride film for a spacer is deposited on the resultant, and a blanket is etched to form a gate spacer 19 of a nitride film material having a buffer oxide film 18 interposed on the sidewall of the gate.
전술한 바와 같은 공정에 따라 형성되는 본 발명에 따른 게이트 스페이서는,우선, 질화막으로 이루어지기 때문에 전기적 절연 측면에서 우수하며, 또한, 게이트 전극과의 사이에 버퍼산화막이 개재되므로 스트레스에 의한 제품 특성의 열화를 방지할 수 있다. 특히, 본 발명의 게이트 스페이서는 버퍼산화막이 외부로 노출되는 형태가 아니라 질화막 스페이서에 의해 덮혀지는 형태이므로 후속하는 콘택 공정에서 버퍼산화막의 식각 손상을 방지할 수 있으며, 그래서, 종래의 문제점은 해결된다.The gate spacer according to the present invention, which is formed according to the above-described process, is made of a nitride film, which is excellent in terms of electrical insulation. Furthermore, since a buffer oxide film is interposed between the gate electrode, Deterioration can be prevented. In particular, the gate spacer of the present invention is not a form in which the buffer oxide film is exposed to the outside but is covered by a nitride film spacer, so that the etching damage of the buffer oxide film can be prevented in a subsequent contact process, so that the conventional problem is solved. .
한편, 전술한 본 발명의 실시예에서는 유동성 산화막으로서 SOG막을 예로 들었지만, SOG막 대신에 버퍼산화막과의 식각 선택비가 상기 SOG막과 유사한 PSG막, BPSG막 및 O3-TEOS막 중에서 선택되는 어느 하나를 이용하는 것도 가능하다.Meanwhile, in the above-described embodiment of the present invention, the SOG film is used as the fluidized oxide film, but instead of the SOG film, the etching selectivity with the buffer oxide film is any one selected from a PSG film, a BPSG film, and an O 3 -TEOS film similar to the SOG film. It is also possible to use.
따라서, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.Therefore, this invention can be implemented in various changes in the range which does not deviate from the summary.
이상에서와 같이, 본 발명은 스페이서용 질화막의 증착 이전에 유동성 절연막을 이용하여 버퍼산화막의 일부를 식각 제거함으로써, 질화막 스페이서의 형성후에 버퍼산화막이 외부로 노출되는 것을 방지하여 후속하는 콘택 공정에서 상기 버퍼산화막의 원치않는 식각을 방지할 수 있으며, 그래서, 공정 마진을 확보할 수 있어서 제조수율을 높일 수 있고, 아울러, 소자의 신뢰성을 확보할 수 있다.As described above, according to the present invention, a portion of the buffer oxide film is etched away using a fluid insulating film before deposition of the nitride film for the spacer, thereby preventing the buffer oxide film from being exposed to the outside after the formation of the nitride film spacer. Undesired etching of the buffer oxide film can be prevented, so that process margin can be secured, manufacturing yield can be increased, and device reliability can be secured.
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| US5817562A (en) * | 1997-01-24 | 1998-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC) |
| KR100213203B1 (en) * | 1996-05-30 | 1999-08-02 | 윤종용 | Semiconductor device with contact hole and process for fabricating the same |
| JPH11214678A (en) * | 1998-01-26 | 1999-08-06 | Matsushita Electron Corp | Semiconductor device and fabrication thereof |
| KR100310823B1 (en) * | 1998-12-15 | 2001-12-17 | 김영환 | Contact hole formation method of semiconductor device |
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| KR100213203B1 (en) * | 1996-05-30 | 1999-08-02 | 윤종용 | Semiconductor device with contact hole and process for fabricating the same |
| US5817562A (en) * | 1997-01-24 | 1998-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC) |
| JPH11214678A (en) * | 1998-01-26 | 1999-08-06 | Matsushita Electron Corp | Semiconductor device and fabrication thereof |
| KR100310823B1 (en) * | 1998-12-15 | 2001-12-17 | 김영환 | Contact hole formation method of semiconductor device |
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