KR100190000B1 - Method for isolation device and dip trench - Google Patents

Abstract

Deep trench and shallow trench combination device isolation structures are described. The present invention provides a device isolation region and a device formation region defined in a semiconductor substrate, and a second trench formed in the semiconductor substrate of the device isolation region, the first trench having a first depth and a second depth shallower than the first depth. And a third trench formed at the second depth on the first trench, and a buried layer of an insulating material embedded in the first trench, the second trench, and the third trench. Therefore, it is possible to improve that the leakage current of the device is increased due to a defect caused by thermal oxidation, thereby improving the reliability of the semiconductor device.

Description

Deep trench and shallow trench combination device isolation structure and manufacturing method

1A to 1D are cross-sectional views illustrating a method of manufacturing a combination device isolation method of a general deep trench device isolation method and a LOCOS method, according to a process sequence.

2 is a cross-sectional view showing a deep trench and a shallow trench combination device isolation structure according to the present invention.

3A to 3D are cross-sectional views illustrating a first embodiment of the deep trench and shallow trench combination device isolation method according to the present invention, in the order of a process.

4a to 4e are cross-sectional views showing a second embodiment of the deep trench and shallow trench combination body separation method according to the present invention in the order of process.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation structure of a semiconductor device and a method for manufacturing the same, and more particularly, to a combination device isolation structure in which two device isolation methods are combined and a method for manufacturing the same.

In general, in a CMOS device such as a Complementary Metal Oxide Semiconductor (CMOS) Static Random Access Memory (SRAM), the source / drain region of a field effect transistor (FET) and a well are connected to each other so that the well does not win. The transistor is formed, and the amplification action of the bipolar transistor causes a latch-up to destroy the device. As a general method of preventing the latch-up phenomenon, a method of separating a device using a deep trench structure, a method of interposing an epitaxial layer between devices, and a distribution of impurity concentrations at a junction are retrograde type. And a method using a silicon on insulator (SOI) structure. The present invention relates to a deep trench device isolation method.

In general, the depth of the deep trench is used for the entire device due to the very deep enough 3㎛~4㎛ the deep trench device difficult to form a separation method N ⁺ / P ⁺ junction of the deep trench element separation wool other hand, N ⁺ / For the junction of N ⁺ or P ⁺ / P ⁺ , two device isolation methods such as LOCOS (LOCal Oxidation of Silicon) method or shallow trench device isolation method are used.

1A to 1D are cross-sectional views illustrating a method of manufacturing a combination device isolation chamber of a general deep trench device isolation method and a LOCOS method, according to a process sequence.

FIG. 1A illustrates a process of forming the deep trench T1, the sacrificial oxide film 14, and the buried layer 16. First, the pad oxide film 10 and the nitride film 12 are sequentially formed on the semiconductor substrate 100. A photoresist pattern (not shown) having a desired size is formed on the nitride film through a process such as photoresist coating, mask exposure, and development, and the nitride film and the pad oxide film are first etched by applying the photoresist pattern to the nitride film 12. A pattern and a pad oxide film 10 pattern, and then using the photoresist pattern and the nitride film 12 / pad oxide film 10 pattern as an etch mask, the semiconductor substrate is anisotropically etched to a predetermined depth, for example, about 3 μm to 4 μm. The deep trench T1 is thereby formed. Subsequently, after removing the photoresist pattern, a sacrificial oxide layer 14, for example, a thermal oxide layer, is formed on the inner wall of the deep trench T1 to remove a damaged portion of the trench during the anisotropic etching process. Subsequently, a buried layer such as polysilicon is deposited on the entire surface of the deep trench T1 to fill the inside of the deep trench T1, and then planarized by an etch back process or a chemical mechanical polishing (CMP) process. The polysilicon 16 is embedded in the deep trench T1 in which 14) is formed. Here, since the deep trench is very deep, a material having excellent step coverage should be used as an insulating material filled in the trench, but the step coverage is poor when the inside of the trench is filled with CVD oxide, for example. Problems inducing voids or seams in the CVD oxide are generated. Therefore, in deep trenches, polysilicon having excellent step coverage is used.

FIG. 1B illustrates a process of forming the capping layer 18, wherein the buried layer 16 filled in the deep trench T1, ie, polycrystalline silicon, is removed during etching of the nitride film for defining the device formation region. By protecting the consume, a portion of the upper portion of the buried layer 16 is oxidized to form a capping layer 18.

FIG. 1C illustrates a process of forming an element formation region, except for an active region in which an element is to be formed through a process such as photoresist coating, mask exposure, and development on the entire surface of the resultant product on which the capping layer 18 is formed. A photoresist pattern (not shown) is formed so that the nitride film 12 of the portion is exposed. Subsequently, the device formation region is defined by etching the nitride layer by applying the photoresist pattern.

FIG. 1D illustrates a process of forming the field oxide film 20. After removing the photoresist pattern of FIG. 1C, the field oxide film 20 is formed by growing a thermal oxide film through a general LOCOS method. At this time, a portion of the polysilicon 16 embedded in the deep trench T1 is also thermally dissipated, thereby forming a very tough oxide film 19 as shown.

FIG. 1E shows a process of completing the device isolation structure combining the deep trench device isolation with the LOCOS device isolation by removing the nitride film.

The problem with the prior art is that when the field oxidation is performed, not only the LOCOS region but also the trench formed region is oxidized. That is, the trench sidewalls are oxidized by thermal oxidation and dislocations are caused due to thermal stress, and such defects are the main cause of the increase in leakage current of the device. In order to improve this, a technique of replacing the LOCOS method with a SEEPOX (Selective Polysilicon Oxidation) method is used. However, since the SEPOX method also thermally oxidizes, it does not completely prevent the formation of defects as described above.

In order to solve this problem, in order to prevent the oxidation of the trench sidewalls during field oxidation, a sacrificial oxide film-forming nitride film of the trench sidewalls is deposited, and a polysilicon is buried on the nitride film, and then a thermal acidic film is grown. See the issue. However, such a technique requires an extra photo process to remove polycrystalline silicon deposited around the trench region in addition to two photo processes, and also removes sidewall nitride from the nitride layer of the active region. There is a disadvantage that the separation structure is poor.

Accordingly, an object of the present invention is to solve the problems of the prior art as described above by using a combination structure of a deep trench embedded with polycrystalline silicon and an oxide film and a shallow trench embedded with an oxide film as a device isolation region. It is to provide a deep trench and shallow trench combination device isolation structure that can fundamentally eliminate defect growth.

Another object of the present invention is to provide an efficient method of manufacturing the deep trench and shallow trench combination device isolation structure, which are new structures.

In order to achieve the above object, the deep trench and shallow trench combination device isolation structure according to the present invention may be formed in a device isolation region, a device formation region, and a semiconductor substrate of the device isolation region defined in a semiconductor substrate. A second trench having a first trench of depth and a second depth shallower than the first depth, a third trench formed at the second depth on top of the first trench, and the first trench, the second trench and the third trench And a buried layer of an insulating material embedded in the trench.

The buried layer of the first trench is made of polycrystalline silicon, the buried layer of the second trench and the third trench is composed of a CVD oxide film.

In order to achieve the above object, a method of manufacturing a deep trench and shallow trench combination device isolation method according to the present invention includes forming an oxide film on a semiconductor substrate, and forming a first trench of a first depth in the semiconductor substrate. Forming, filling the inside of the first trench with a first buried layer, forming a first insulating film, a second insulating film, and a third insulating film on the entire surface of the resultant after the first buried layer is formed; Forming a second trench and a third trench having a second depth different from the first trench in the upper portion of the trench and the semiconductor substrate, and filling the second trench and the third trench inside with a second buried layer. It is characterized by comprising a step.

Therefore, according to the deep trench and shallow trench combination device isolation structure and a manufacturing method thereof according to the present invention, since the insulating material is embedded in the trench structure, the problem occurring during the conventional thermal oxidation can be fundamentally solved.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a view showing a deep trench and shallow trench combination device isolation structure according to the present invention.

Referring to FIG. 2, first, an isolation region and a device formation region are defined in the semiconductor substrate 100, and deep trenches T1 and shallow trenches T2 having different depths are formed in the semiconductor substrate of the isolation region. Sacrificial oxide films 36 and 40 are formed on inner walls of the deep trenches T1 and shallow trenches T2, respectively, and the deep trenches T1 and shallow where the sacrificial oxide films 36 and 46 are formed. A first buried layer 38 made of polycrystalline silicon and a second buried layer 42 made of a CVD oxide film are formed in the trench T2.

3A to 3D are cross-sectional views illustrating a first embodiment of a deep trench and shallow trench combination device isolation method according to an exemplary embodiment of the present invention.

3A illustrates a process of forming the first insulating film 30, the second insulating film 32, the third insulating film 34, and the deep trench T1. First, the first insulating film 30 is formed on the semiconductor substrate 100. A pad oxide film, a second insulating film 32, a nitride film, and a third insulating film 34, a CVD oxide film is formed to a predetermined thickness, and then laminated. Then, photoresist coating and mask exposure are performed on the third insulating film 34. And a first photoresist pattern PR1 having a predetermined size by defining a separation region through a process such as development. Next, by applying the first photoresist pattern PR1, the third insulating film 34, the second insulating film 32, the first insulating film 30, and the semiconductor substrate are anisotropic to a predetermined depth such as 3 μm to 4 μm. Etching forms a deep trench T1 as shown.

FIG. 3B illustrates a process of forming the sacrificial oxide layer 36, the first buried layer 38, and the second photoresist pattern PR2. First, the first photoresist pattern is removed, and then the trenches are formed in the anisotropic etching process. A sacrificial oxide film 36, for example, a thermal oxide film, is grown on the inner wall of the deep trench T1 to a predetermined thickness to remove the damaged inner wall. Subsequently, the sacrificial oxide layer 36 is formed by filling the inside of the deep trench T1 by infiltrating the first buried layer 38, for example, polysilicon, on the entire surface of the resultant, and then performing planarization by performing an etch back process or a CMP process. The polysilicon 38 is embedded in the deep trench T1. The second photoresist pattern PR2 defining the active region is formed on the entire surface of the resultant through a process such as photoresist coating, mask exposure, and development.

FIG. 3C illustrates a process of forming the shallow trenches T2 and the sacrificial oxide film 40. First, the third insulating film 34, the second insulating film 32, and the first insulating film are applied by applying the second photoresist pattern. After etching the insulating film 30 in sequence, the second photoresist pattern is removed. Next, by using the etched third insulating film 34, the second insulating film 32 and the first insulating film 30 as a mask for etching, the semiconductor substrate is anisotropically etched to a predetermined depth, for example, 1 탆 to 2 탆. The shallow trench T2 as shown is formed. Subsequently, a sacrificial oxide film 40, for example, a thermal oxide film, is grown on the inner wall of the shallow trench T2 by a predetermined thickness in order to remove the damaged inner wall of the trench during the anisotropic etching process. In this case, a capping layer 41 having a predetermined thickness is formed on the polycrystalline silicon, which is the first buried layer 38 inside the deep trench T1, when the sacrificial oxide film is formed on the shallow trench T2. The capping layer 41 is made of a polycrystalline oxide film in which polycrystalline silicon, which is a first buried layer, is oxidized.

FIG. 3d illustrates a process of forming the second buried layer 42. A second process is performed to fill a portion of the deep trench T1 and the inside of the shallow trench T2 on the entire surface of the resultant after the process of FIG. 3c. After the buried layer 42 is formed, for example, a CVD oxide film, the oxide film 42 is buried by performing a CMP process to planarize it. Next, the third insulating film, the second insulating film, and the first insulating film are sequentially removed to fill the deep trench T1 with the polysilicon 38 and the oxide film 42, and the shallow trench T2 with the oxide film ( The combination device isolation structure 42 is embedded.

4A to 4E are cross-sectional views illustrating a second embodiment of the deep trench and shallow trench combination device isolation method according to the present invention, in the order of a process.

4A shows a process of forming the oxide film 31 and the deep trench T1. First, the oxide film 31 is formed to a predetermined thickness on the semiconductor substrate 100, and then the oxide film 31 is formed on the photoresist. The first photoresist pattern PR1 having a predetermined size for defining the isolation region is formed through a process such as coating, mask exposure, and development. Next, by applying the first photoresist pattern PR1 to anisotropically etch the semiconductor substrate to the oxide film 31 and the first depth, for example, about 3 μm to 4 μm, the deep trenches T1 and first trenches as shown in the drawing. To form.

4B illustrates a process of forming the sacrificial oxide layer 36 and the first buried layer 38. First, the first photoresist pattern is removed, and then the sacrificial oxide layer 36 is sacrificed to enhance damage to the inner wall of the trench during the anisotropic etching process. An oxide film 36, for example, a thermal oxide film, is grown to a predetermined thickness on the inner wall of the deep trench T1. Subsequently, the sacrificial oxide layer 36 is formed by depositing the first buried layer 38, for example, polysilicon, on the entire surface of the resultant to fill the deep trench T1, and then performing planarization by an etch back process or a CMP process. The polysilicon 38 is embedded in the deep trench T1.

4C illustrates a process of forming the first insulating film 30, the second insulating film 32, the third insulating film 34, and the second photoresist pattern PR2. First, an etching mask is formed when the deep trench is formed. After removing the used oxide film, the pad oxide film was formed by the first insulating film 30 on the entire surface of the resultant, the nitride film was formed by the second insulating film 32, and the CVD oxide film was formed by the third insulating film 34, respectively, and then laminated. A second photoresist pattern PR2 having a predetermined size for defining an active region is formed on the third insulating layer 34 through photoresist coating, mask exposure, and development. In this case, the second photoresist pattern PR2 is formed to expose the periphery of the deep trench T1 such that the shallow trench is also formed on the deep trench T1 in a subsequent process. Next, a predetermined thickness of the exposed first investment layer 38 is oxidized to form a capping layer 39.

FIG. 4D illustrates a process of forming the shallow trench T2. The third insulating film 34, the second insulating film 32, and the first insulating film 30 are applied by applying the second photoresist pattern PR2. And an anisotropic etching of the semiconductor substrate to a second depth smaller than the first depth, for example, 1 µm to 2 µm, to form a shallow trench T2 (second trench) as shown. At this time, when the shallow trench T2 is formed, a part of the polysilicon embedded in the deep trench T1 is also etched, and the upper portion of the deep trench T1 is shallow trenches T3 and third of the second depth. And a pillar of the sacrificial oxide film 36 formed on the inner wall of the deep trench T1.

FIG. 4E illustrates a process of forming the sacrificial oxide film 40 and the second buried layer 42. First, the second photoresist pattern is removed, and then the sacrificial oxide film for removing damage to the inner wall of the trench during the anisotropic etching process. (40) For example, a thermal oxide film is grown to a predetermined thickness on the inner walls of the shallow trenches T2 and T3. Subsequently, a second buried layer 42 for filling the inside of the shallow trenches T2 and T3, for example, a CVD oxide film is formed on the entire surface of the resultant, and then the oxide film 42 is embedded by planarization by performing a CMP process. Next, by sequentially removing the third insulating film 34, the second insulating film 32, and the first insulating film 30, the polysilicon 38 is embedded in the deep trench T1, and the shallow trench T2 is formed. , T3) completes the combined device isolation structure in which the oxide film 42 is embedded.

Therefore, according to the deep trench and shallow trench combination device isolation structure according to the present invention and a method for manufacturing the same, the growth of defects due to thermal oxidation to form a conventional isolation region by fundamentally embedding polysilicon and an oxide film inside the trench is essential. Not only can it be prevented, it is possible to realize device isolation by combining a deep trench and a shallow trench in a very simple manner.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (7)

A second trench formed in the device isolation region and the device formation region defined in the semiconductor substrate, the second trench having a first trench of a first depth and a second depth shallower than the first depth; The deep trench combination combination of the trench is provided with the 3rd trench formed in the said 2nd depth in the upper part of the trench, and the buried layer of the insulating material embedded in the said 1st trench, the 2nd trench, and the 3rd trench. Device isolation structure. The deep trench and shallow trench combination device isolation structure of claim 1, wherein the buried layer of the first trench is polysilicon, the second trench, and the third trench is a CVD oxide film. Forming an oxide film on the semiconductor substrate, forming a first trench of a first depth in the semiconductor substrate, embedding the inside of the first trench into a first buried layer, and after forming the first buried layer Forming a first insulating film, a first insulating film, and a third insulating film on the entire surface, and forming a second trench and a third trench having a second depth different from that of the first trench in the upper portion of the first trench and the semiconductor substrate. And forming a second trench and filling the inside of the second trench and the third trench with a second buried layer. The method of claim 10, wherein the first trench is a deep trench having a depth of about 3㎛ 4㎛, the second trench and the third trench is a shallow trench having a depth of about 1㎛ 2㎛ Deep trench and shallow trench combination type device manufacturing method. 12. The method of claim 11, wherein the first insulating film, the second insulating film and the third insulating film, the pad oxide film, the nitride film, and the CVD oxide film are formed. The method of claim 12, wherein the filling of the inside of the first trench with the first buried layer comprises forming a sacrificial oxide film on an inner wall of the first trench after forming the first trench, and forming the sacrificial oxide film. A method of manufacturing a deep trench and shallow trench combination device isolation method comprising depositing a polysilicon layer, which is a first buried layer, on an entire surface of a resultant, and then performing an etch back or CMP process. The method of claim 13, wherein the filling of the second trench and the third trench inside with the second buried layer is performed after the formation of the second trench and the third trench and on the inner walls of the second trench and the third trench. And forming an oxide film as a second buried layer on the entire surface of the product on which the sacrificial oxide film is formed, and then performing an etch back or CMP process.