JP2577864B2 - Method for forming fine contact hole in semiconductor device - Google Patents
Method for forming fine contact hole in semiconductor deviceInfo
- Publication number
- JP2577864B2 JP2577864B2 JP5249431A JP24943193A JP2577864B2 JP 2577864 B2 JP2577864 B2 JP 2577864B2 JP 5249431 A JP5249431 A JP 5249431A JP 24943193 A JP24943193 A JP 24943193A JP 2577864 B2 JP2577864 B2 JP 2577864B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- oxide film
- contact hole
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は微細パターンが要求され
るＤＲＡＭ、ＳＲＡＭ、ＡＳＩＣ等の高集積半導体素子
の微細コンタクトホール形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming fine contact holes in highly integrated semiconductor devices such as DRAMs, SRAMs, ASICs, etc., which require a fine pattern.
【０００２】[0002]
【従来の技術】一般的に半導体素子の集積度が増加する
程チップ（chip）上の最小線幅はこれに従って減少し、
単位セルの面積も減少するようになる。このような最小
線幅の減少により線間の間隔も減少するため、線間にコ
ンタクト領域を形成するには多くの困難が伴った。2. Description of the Related Art Generally, as the degree of integration of semiconductor devices increases, the minimum line width on a chip decreases accordingly.
The area of the unit cell also decreases. Such a decrease in the minimum line width also reduces the distance between the lines, and thus it has been difficult to form a contact region between the lines.
【０００３】従来の微細コンタクトホール形成方法は自
己整列コンタクト（self align contact）方法を用いて
いるが、トポロジ（topology）が甚だしい場合、コンタ
クトホールの蝕刻時にアスペクト比が大きいため蝕刻工
程に困難があり、ＤＲＡＭセルの場合はワード線とビッ
ト線の短絡、ワード線又はビット線の電荷貯蔵電極との
短絡、断差による線の短絡、コンタクト抵抗の増加等、
幾多の工程上の困難を経験してきた。A conventional method for forming a fine contact hole uses a self-aligned contact method. However, when the topology is severe, the etching process is difficult due to a large aspect ratio when the contact hole is etched. In the case of a DRAM cell, a short circuit between a word line and a bit line, a short circuit between a word line or a bit line and a charge storage electrode, a short circuit between lines due to a gap, an increase in contact resistance,
It has experienced a number of process difficulties.
【０００４】本発明は、上記の問題に対処するため、高
いトポロジと微細パターンを有する高集積半導体素子の
コンタクトホール形成時にバリアとして作用する絶縁膜
側壁にポリシリコンパッドを形成して同ポリシリコンパ
ッドが絶縁膜と共に蝕刻バリアとして作用するようにす
ることにより、蝕刻マスクのパターンより小さい幅を有
するコンタクトホールを形成する方法を提供することを
目的とする。In order to address the above-mentioned problems, the present invention forms a polysilicon pad on a side wall of an insulating film which acts as a barrier when forming a contact hole of a highly integrated semiconductor device having a high topology and a fine pattern. It is an object of the present invention to provide a method for forming a contact hole having a width smaller than that of a pattern of an etching mask by allowing the substrate to act as an etching barrier together with an insulating film.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
に、本発明による半導体素子の微細コンタクトホール形
成方法は、半導体基板のコンタクト領域を含む表面に酸
化膜を蒸着する工程、該酸化膜より蝕刻率が小さい絶縁
膜を同酸化膜の表面に蒸着する工程、前記絶縁膜の表面
に感光膜を塗布した後マスキング工程にて所望の感光膜
パターンを形成する工程、前記感光膜パターンを利用し
て前記絶縁膜の前記コンタクト領域に対応する部分を非
等方性蝕刻し、次いでその絶縁膜の蝕刻された部分に露
出した前記酸化膜の部分を等方性蝕刻により絶縁膜の下
側まで回り込んで除去する工程、前記絶縁膜上に残存し
ている前記感光膜を除去し前記絶縁膜を露出する工程、
前記露出した絶縁膜と前記蝕刻により絶縁膜の下側まで
回り込んで露出した前記酸化膜の表面に所定の厚さでポ
リシリコン膜を蒸着する工程、前記酸化膜が露出するよ
う前記ポリシリコン膜を非等方性蝕刻することにより、
前記絶縁膜の側壁及び前記絶縁膜の下側まで回り込んで
露出した前記酸化膜の側壁にポリシリコンパッドを形成
する工程、及び前記絶縁膜とポリシリコンパッドを蝕刻
バリアとして利用して前記コンタクトホール領域の酸化
膜を蝕刻してコンタクトホールを形成する工程を含んで
成ることを特徴とする。In order to achieve the above object, a method for forming a fine contact hole in a semiconductor device according to the present invention comprises the steps of: depositing an oxide film on a surface of a semiconductor substrate including a contact region; Depositing an insulating film having a low etching rate on the surface of the oxide film, forming a desired photosensitive film pattern in a masking process after applying a photosensitive film on the surface of the insulating film, using the photosensitive film pattern; the part corresponding to the contact area of the insulating film Te non
Isotropic etching, and then exposing the etched portion of the insulating film
The exposed portion of the oxide film is etched under the insulating film by isotropic etching.
Removing goes around to the side, the step of exposing the insulating film to remove the photoresist remaining on the insulating film,
By the said exposed insulating film etched to the bottom side of the insulating film
Depositing a polysilicon film with a predetermined thickness on the surface of the oxide film exposed goes around, by pre-Symbol oxide film is anisotropically etching the polysilicon film so as to expose,
Around the side wall of the insulating film and below the insulating film.
Forming a polysilicon pad on the exposed sidewall of the oxide film ; and forming a contact hole by etching the oxide film in the contact hole region using the insulating film and the polysilicon pad as an etching barrier. It is characterized by comprising.
【０００６】[0006]
【実施例】以下、添付図面を参照して本発明の実施例を
詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
【０００７】先ず、図１に示したように、半導体基板１
の表面に素子分離酸化膜２、ゲート酸化膜３、ゲート電
極であるワード線４、ソース電極６Ａ、ドレイン電極６
Ｂを形成した後に酸化膜５を蒸着する。First, as shown in FIG.
Element isolation oxide film 2, gate oxide film 3, word line 4 as a gate electrode, source electrode 6A, drain electrode 6
After forming B, an oxide film 5 is deposited.
【０００８】次に、図２に示したように、酸化膜５の表
面に更に酸化膜７を蒸着し、この酸化膜７の表面に同酸
化膜７より蝕刻率が小さいシリコン窒化膜８を蒸着し、
該シリコン窒化膜８の表面に感光膜９を塗布した後、マ
スキング工程にて所望のパターンを形成する。Next, as shown in FIG. 2, an oxide film 7 is further deposited on the surface of the oxide film 5, and a silicon nitride film 8 having an etching rate smaller than that of the oxide film 7 is deposited on the surface of the oxide film 7. And
After coating the photosensitive film 9 on the surface of the silicon nitride film 8, a desired pattern is formed in a masking step.
【０００９】次いで、図３に示したように、上記感光膜
パターン９を利用して上記シリコン窒化膜８の前記コン
タクト領域に対応する部分を非等方的に乾式蝕刻し、次
いでそのシリコン窒化膜８の蝕刻された部分に露出した
酸化膜７の部分を等方的に湿式蝕刻してシリコン窒化膜
８の下側まで回り込んで除去する。[0009] Then, as shown in FIG. 3, the con of the silicon nitride film 8 by using the photoresist pattern 9
And dry etching the portion corresponding to the tact region anisotropically, following
Ide isotropically wet etched to silicon nitride film portions of <br/> oxide film 7 exposed to the etched portion of the silicon nitride film 8
8 and wrap around to remove .
【００１０】その後に、図４に示したように、上記感光
膜９を除去して露出されたシリコン窒化膜８とその下側
まで回り込んで蝕刻された酸化膜７の表面にポリシリコ
ン膜１０を蒸着する。次いで、図５に示したように、酸
化膜７及びシリコン窒化膜８が露出するまでポリシリコ
ン膜１０を非等方性蝕刻することにより、シリコン窒化
膜８の側壁及びシリコン窒化膜８の下側まで回り込んで
露出した酸化膜７の側壁にポリシリコンパッド１０Ａを
形成する。次いで、図６に示したように、コンタクトホ
ール領域の酸化膜７と酸化膜５を順次蝕刻してコンタク
トホールを形成する。このとき、シリコン窒化膜８の側
壁に形成されたポリシリコンパッド１０Ａが蝕刻バリア
として作用してコンタクトホールマスクのパターンより
小さい幅を有するコンタクトホールが形成される。この
場合、ポリシリコンパッド１０Ａがシリコン窒化膜８の
下側まで回り込んで引っかかった構造になっているの
で、微細でありながら、安定した蝕刻バリアとして役目
を果たしている。 Thereafter, as shown in FIG. 4, the photosensitive film 9 is removed and the exposed silicon nitride film 8 and the underlying silicon nitride film 8 are removed.
Then , a polysilicon film 10 is deposited on the surface of the oxide film 7 which has been etched. Then, as shown in FIG. 5, by acid <br/> of film 7 and the silicon nitride film 8 is anisotropically etching the polysilicon film 10 to expose the silicon nitride
Around the side wall of the film 8 and below the silicon nitride film 8
A polysilicon pad 10A is formed on the exposed side wall of oxide film 7 . Next, as shown in FIG. 6, the oxide film 7 and the oxide film 5 in the contact hole region are sequentially etched to form a contact hole. At this time, the polysilicon pad 10A formed on the side wall of the silicon nitride film 8 acts as an etching barrier to form a contact hole having a width smaller than the pattern of the contact hole mask. this
In this case, the polysilicon pad 10A is
It has a structure that goes down to the bottom and gets caught
And serves as a stable, yet fine etching barrier
Plays.
【００１１】[0011]
【発明の作用及び効果】本発明は、比較的に簡単な工程
により高集積半導体素子の製造工程にて非常に小さい線
間隔のコンタクトホールを形成することにより、度々発
生するワード線、ビット線等の電導層との短絡を防止で
きるよう工程に余裕を与えることができる。従って、本
発明は高集積半導体素子の微細コンタクトホールを容易
に形成できるので、素子の歩留まりを向上させるだけで
なく、素子の信頼性を向上させる効果がある。According to the present invention, a word line, a bit line, etc., which are frequently generated, are formed by forming contact holes having a very small line interval in a manufacturing process of a highly integrated semiconductor device by a relatively simple process. Can be given a margin so that a short circuit with the conductive layer can be prevented. Therefore, the present invention can easily form a fine contact hole of a highly integrated semiconductor device, and thus has an effect of improving not only the yield of the device but also the reliability of the device.
【図１】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第１工程を示す図。FIG. 1 is a diagram showing a first step of a method for forming a fine contact hole in a semiconductor device according to the present invention.
【図２】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第２工程を示す図。FIG. 2 is a view showing a second step of the method for forming a fine contact hole in a semiconductor device according to the present invention.
【図３】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第３工程を示す図。FIG. 3 is a view showing a third step of the method for forming fine contact holes in a semiconductor device according to the present invention.
【図４】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第４工程を示す図。FIG. 4 is a view showing a fourth step of the method for forming a fine contact hole in a semiconductor device according to the present invention.
【図５】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第５工程を示す図。FIG. 5 is a view showing a fifth step of the method for forming fine contact holes in a semiconductor device according to the present invention.
【図６】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第６工程を示す図。FIG. 6 is a view showing a sixth step of the method for forming fine contact holes in a semiconductor device according to the present invention.
１…半導体基板、２…素子分離酸化膜、３…ゲート酸化
膜、４…ワード線、５、７…酸化膜，６Ａ…ソース電
極、６Ｂ…ドレイン電極、８…シリコン窒化膜、９…感
光膜、１０…ポリシリコン膜、１０Ａ…ポリシリコンパ
ッドDESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation oxide film, 3 ... Gate oxide film, 4 ... Word line, 5, 7 ... Oxide film, 6A ... Source electrode, 6B ... Drain electrode, 8 ... Silicon nitride film, 9 ... Photosensitive film 10 ... polysilicon film, 10A ... polysilicon pad
───────────────────────────────────────────────────── フロントページの続き (72)発明者 ドン ヤール キュム 大韓民国 キュンサンブクド チュンド クン リ−セオミュン シンチョン ２ −ドン 462 (56)参考文献 特開 平６−85086（ＪＰ，Ａ) 特開 平４−5823（ＪＰ，Ａ) 特開 平３−295230（ＪＰ，Ａ) 特開 平３−178129（ＪＰ，Ａ) 特開 昭63−102340（ＪＰ，Ａ) 特開 昭60−160653（ＪＰ，Ａ) ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Dong Yar Kum Kumsanbukdo Chundung Kung Li-Seomyun Sinchon 2-Dong 462 (56) References JP-A-6-85086 (JP, A) JP-A-4-5823 ( JP, A) JP-A-3-295230 (JP, A) JP-A-3-178129 (JP, A) JP-A-63-102340 (JP, A) JP-A-60-160653 (JP, A)
Claims (3)
タクトホールを形成する方法であって、 半導体基板のコンタクト領域を含む表面に酸化膜を蒸着
する工程、 該酸化膜より蝕刻率が小さい絶縁膜を同酸化膜の表面に
蒸着する工程、 前記絶縁膜の表面に感光膜を塗布した後、マスキング工
程にて所望の感光膜パターンを形成する工程、 前記感光膜パターンを利用して前記絶縁膜の前記コンタ
クト領域に対応する部分を非等方性蝕刻し、次いでその
絶縁膜の蝕刻された部分に露出した前記酸化膜の部分を
等方性蝕刻により絶縁膜の下側まで回り込んで除去する
工程、 前記絶縁膜上に残存している前記感光膜を除去し前記絶
縁膜を露出する工程、 前記露出した絶縁膜と前記蝕刻により絶縁膜の下側まで
回り込んで露出した前記酸化膜の表面に所定の厚さでポ
リシリコン膜を蒸着する工程、前 記酸化膜が露出するよう前記ポリシリコン膜を非等方
性蝕刻することにより、前記絶縁膜の側壁及び前記絶縁
膜の下側まで回り込んで露出した前記酸化膜の側壁にポ
リシリコンパッドを形成する工程、及び 前記絶縁膜とポリシリコンパッドを蝕刻バリアとして利
用して、前記コンタクトホール領域の酸化膜を蝕刻して
コンタクトホールを形成する工程を含んで成ることを特
徴とする半導体素子の微細コンタクトホール形成方法。1. A method at the manufacturing process of a semiconductor device for forming a fine contact hole, depositing an oxide film on the surface including the contact region of the semiconductor substrate, an insulating etch rate than the oxide film is small film Depositing a photosensitive film on the surface of the insulating film, forming a desired photosensitive film pattern in a masking process after applying a photosensitive film on the surface of the insulating film, using the photosensitive film pattern to form the insulating film . The contour
A portion corresponding to the defect area and non-isotropic etching, and then the
The portion of the oxide film exposed at the etched portion of the insulating film is removed.
Step of wraps around at removed by isotropic etching to the lower insulating film, the step of exposing the insulating film to remove the photoresist remaining on the insulating film, by the said exposed insulating film etching To the lower side of the insulating film
In the surface of the predetermined thickness of the wrap around is exposed the oxide film step of depositing a polysilicon film, by pre-Symbol oxide film is anisotropically etching the polysilicon film so as to expose, in the insulating film Side walls and the insulation
Forming a polysilicon pad on the side wall of the oxide film that is exposed to the lower side of the film, and etching the oxide film in the contact hole region using the insulating film and the polysilicon pad as an etching barrier. Forming a fine contact hole in a semiconductor device , comprising the step of forming a contact hole by using the method.
を特徴とする請求項１に記載した半導体素子の微細コン
タクトホール形成方法。2. The method according to claim 1, wherein the insulating film is a silicon nitride film.
請求項１に記載した半導体素子の微細コンタクトホール
形成方法。3. The method of claim 1, wherein the oxide film is deposited in two layers.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920018285A KR950010852B1 (en) | 1992-10-06 | 1992-10-06 | Fine contact patterning method of semiconductor device |
| KR1992-18850 | 1992-10-13 | ||
| KR92018850A KR970008353B1 (en) | 1992-10-13 | 1992-10-13 | Micro-contact formation of vlsi semiconductor elements |
| KR1992-18285 | 1992-10-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06244129A JPH06244129A (en) | 1994-09-02 |
| JP2577864B2 true JP2577864B2 (en) | 1997-02-05 |
Family
ID=26629289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5249431A Expired - Fee Related JP2577864B2 (en) | 1992-10-06 | 1993-10-05 | Method for forming fine contact hole in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2577864B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60160653A (en) * | 1984-02-01 | 1985-08-22 | Hitachi Ltd | Manufacture of semiconductor device |
| JP2765133B2 (en) * | 1989-12-06 | 1998-06-11 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
| JPH0736394B2 (en) * | 1990-03-23 | 1995-04-19 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
-
1993
- 1993-10-05 JP JP5249431A patent/JP2577864B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06244129A (en) | 1994-09-02 |
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