JPH06244129A - Method for forming fine contact hole of semiconductor element - Google Patents

Method for forming fine contact hole of semiconductor element

Info

Publication number
JPH06244129A
JPH06244129A JP5249431A JP24943193A JPH06244129A JP H06244129 A JPH06244129 A JP H06244129A JP 5249431 A JP5249431 A JP 5249431A JP 24943193 A JP24943193 A JP 24943193A JP H06244129 A JPH06244129 A JP H06244129A
Authority
JP
Japan
Prior art keywords
film
contact hole
forming
oxide film
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5249431A
Other languages
Japanese (ja)
Other versions
JP2577864B2 (en
Inventor
Jong Kim
キム ジョン
Yo-Hwan Ko
ファン コ ヨ
Dong-Ryul Keum
ヤール キュム ドン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019920018285A external-priority patent/KR950010852B1/en
Priority claimed from KR92018850A external-priority patent/KR970008353B1/en
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of JPH06244129A publication Critical patent/JPH06244129A/en
Application granted granted Critical
Publication of JP2577864B2 publication Critical patent/JP2577864B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To provide a method for forming contact holes having width smaller than the patterns of an etching mask. CONSTITUTION: In the method for forming fine contact holes on a highly integrated semiconductor element such a DRAM, SRAM and an ASIC requiring fine patterns, a polysilicon pad 10A acting as an etching barrier is formed on the sidewall of a silicon nitride film 8 at the time of etching for forming contact holes, so that fine contact holes smaller than contact mask patterns can be formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は微細パターンが要求され
るDRAM、SRAM、ASIC等の高集積半導体素子
の微細コンタクトホール形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact hole in a highly integrated semiconductor device such as DRAM, SRAM, ASIC, etc. which requires a fine pattern.

【0002】[0002]

【従来の技術】一般的に半導体素子の集積度が増加する
程チップ(chip)上の最小線幅はこれに従って減少し、
単位セルの面積も減少するようになる。このような最小
線幅の減少により線間の間隔も減少するため、線間にコ
ンタクト領域を形成するには多くの困難が伴った。
2. Description of the Related Art Generally, as the degree of integration of semiconductor devices increases, the minimum line width on a chip decreases accordingly.
The area of the unit cell is also reduced. Due to such a decrease in the minimum line width, the distance between the lines is also reduced, so that it is difficult to form a contact region between the lines.

【0003】従来の微細コンタクトホール形成方法は自
己整列コンタクト(self align contact)方法を用いて
いるが、トポロジ(topology)が甚だしい場合、コンタ
クトホールの蝕刻時にアスペクト比が大きいため蝕刻工
程に困難があり、DRAMセルの場合はワード線とビッ
ト線の短絡、ワード線又はビット線の電荷貯蔵電極との
短絡、断差による線の短絡、コンタクト抵抗の増加等、
幾多の工程上の困難を経験してきた。
The conventional method of forming a fine contact hole uses a self align contact method. However, if the topology is severe, the contact hole has a large aspect ratio and the etching process is difficult. In the case of a DRAM cell, a short circuit between a word line and a bit line, a short circuit between a word line or a bit line and a charge storage electrode, a short circuit due to a gap, an increase in contact resistance, etc.
We have experienced numerous process difficulties.

【0004】本発明は、上記の問題に対処するため、高
いトポロジと微細パターンを有する高集積半導体素子の
コンタクトホール形成時にバリアとして作用する絶縁膜
側壁にポリシリコンパッドを形成して同ポリシリコンパ
ッドが絶縁膜と共に蝕刻バリアとして作用するようにす
ることにより、蝕刻マスクのパターンより小さい幅を有
するコンタクトホールを形成する方法を提供することを
目的とする。
To solve the above problems, the present invention forms a polysilicon pad on the sidewall of an insulating film that acts as a barrier when forming a contact hole of a highly integrated semiconductor device having a high topology and a fine pattern, and the same polysilicon pad is formed. It is an object of the present invention to provide a method for forming a contact hole having a width smaller than the pattern of the etching mask by allowing the film to act as an etching barrier together with the insulating film.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明による半導体素子の微細コンタクトホール形
成方法は、半導体基板のコンタクト領域を含む表面に酸
化膜を蒸着する工程、該酸化膜より蝕刻率が小さい絶縁
膜を同酸化膜の表面に蒸着する工程、前記絶縁膜の表面
に感光膜を塗布した後マスキング工程にて所望のパター
ンを形成して前記酸化膜の一部を蝕刻により除去する工
程、前記酸化膜上に残存している前記感光膜を除去する
工程、蝕刻によりその一部を除去した前記酸化膜と絶縁
膜の表面に所定の厚さでポリシリコン膜を蒸着する工
程、別途のマスクを使用せず前記酸化膜が露出するよう
前記ポリシリコン膜を非等方性蝕刻することにより前記
絶縁膜の側壁にポリシリコンパッドを形成する工程、及
び前記絶縁膜とポリシリコンパッドを蝕刻バリアとして
利用して前記コンタクトホール領域の酸化膜を蝕刻して
コンタクトホールを形成する工程から成ることを特徴と
する。
In order to achieve the above object, a method of forming a fine contact hole of a semiconductor device according to the present invention comprises a step of depositing an oxide film on a surface of a semiconductor substrate including a contact region, A step of depositing an insulating film having a low etching rate on the surface of the oxide film, a photosensitive film is applied on the surface of the insulating film, and then a desired pattern is formed by a masking process to remove a part of the oxide film by etching. A step of removing the photosensitive film remaining on the oxide film, a step of depositing a polysilicon film with a predetermined thickness on the surface of the oxide film and the insulating film, a portion of which is removed by etching. Forming a polysilicon pad on a sidewall of the insulating film by anisotropically etching the polysilicon film to expose the oxide film without using a separate mask; and Characterized by comprising the step of forming the contact hole by using a silicon pad as an etching barrier etching the oxide film of the contact hole area.

【0006】[0006]

【実施例】以下、添付図面を参照して本発明の実施例を
詳細に説明する。
Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

【0007】先ず、図1に示したように、半導体基板1
の表面に素子分離酸化膜2、ゲート酸化膜3、ゲート電
極であるワード線4、ソース電極6A、ドレイン電極6
Bを形成した後に酸化膜5を蒸着する。
First, as shown in FIG. 1, the semiconductor substrate 1
A device isolation oxide film 2, a gate oxide film 3, a word line 4 as a gate electrode, a source electrode 6A, and a drain electrode 6 on the surface of
After forming B, the oxide film 5 is deposited.

【0008】次に、図2に示したように、酸化膜5の表
面に更に酸化膜7を蒸着し、この酸化膜7の表面に同酸
化膜7より蝕刻率が小さいシリコン窒化膜8を蒸着し、
該シリコン窒化膜8の表面に感光膜9を塗布した後、マ
スキング工程にて所望のパターンを形成する。
Next, as shown in FIG. 2, an oxide film 7 is further deposited on the surface of the oxide film 5, and a silicon nitride film 8 having a smaller etching rate than the oxide film 7 is deposited on the surface of the oxide film 7. Then
After applying the photosensitive film 9 on the surface of the silicon nitride film 8, a desired pattern is formed in a masking process.

【0009】次いで、図3に示したように、上記感光膜
パターン9を利用して上記シリコン窒化膜8を乾式蝕刻
し、酸化膜7の一部を湿式蝕刻する。
Next, as shown in FIG. 3, the silicon nitride film 8 is dry-etched using the photosensitive film pattern 9 and a part of the oxide film 7 is wet-etched.

【0010】その後に、図4に示したように、上記感光
膜9を除去して露出されたシリコン窒化膜8とその一部
を蝕刻された酸化膜7の表面にポリシリコン膜10を蒸
着する。次いで、図5に示したように、コンタクトホー
ル領域の酸化膜7と酸化膜5を順次蝕刻してコンタクト
ホールを形成する。このとき、シリコン窒化膜8の側壁
に形成されたポリシリコンパッド10Aが蝕刻バリアと
して作用してコンタクトホールマスクのパターンより小
さい幅を有するコンタクトホールが形成される。
Thereafter, as shown in FIG. 4, the photosensitive film 9 is removed and a polysilicon film 10 is deposited on the exposed surface of the silicon nitride film 8 and the oxide film 7 which is partially etched. . Next, as shown in FIG. 5, the oxide film 7 and the oxide film 5 in the contact hole region are sequentially etched to form a contact hole. At this time, the polysilicon pad 10A formed on the side wall of the silicon nitride film 8 acts as an etching barrier to form a contact hole having a width smaller than the pattern of the contact hole mask.

【0011】[0011]

【発明の作用及び効果】本発明は、比較的に簡単な工程
により高集積半導体素子の製造工程にて非常に小さい線
間隔のコンタクトホールを形成することにより、度々発
生するワード線、ビット線等の電導層との短絡を防止で
きるよう工程に余裕を与えることができる。従って、本
発明は高集積半導体素子の微細コンタクトホールを容易
に形成できるので、素子の歩留まりを向上させるだけで
なく、素子の信頼性を向上させる効果がある。
According to the present invention, word lines, bit lines, etc., which are frequently generated by forming contact holes with very small line intervals in the manufacturing process of highly integrated semiconductor devices by a relatively simple process. It is possible to give a margin to the process so as to prevent a short circuit with the conductive layer. Therefore, the present invention can easily form a fine contact hole of a highly integrated semiconductor device, and thus has an effect of improving not only the yield of the device but also the reliability of the device.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第1工程を示す図。
FIG. 1 is a diagram showing a first step of a method for forming a fine contact hole in a semiconductor device according to the present invention.

【図2】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第2工程を示す図。
FIG. 2 is a diagram showing a second step of the method for forming a fine contact hole of a semiconductor device according to the present invention.

【図3】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第3工程を示す図。
FIG. 3 is a diagram showing a third step of the method for forming a fine contact hole in a semiconductor device according to the present invention.

【図4】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第4工程を示す図。
FIG. 4 is a diagram showing a fourth step of the method for forming a fine contact hole of a semiconductor device according to the present invention.

【図5】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第5工程を示す図。
FIG. 5 is a diagram showing a fifth step of the method for forming a fine contact hole in a semiconductor device according to the present invention.

【図6】 本発明による半導体素子の微細コンタクトホ
ール形成方法の第6工程を示す図。
FIG. 6 is a diagram showing a sixth step of the method for forming a fine contact hole in a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

1…半導体基板、2…素子分離酸化膜、3…ゲート酸化
膜、4…ワード線、5、7…酸化膜,6A…ソース電
極、6B…ドレイン電極、8…シリコン窒化膜、9…感
光膜、10…ポリシリコン膜、10A…ポリシリコンパ
ッド
1 ... Semiconductor substrate, 2 ... Element isolation oxide film, 3 ... Gate oxide film, 4 ... Word line, 5, 7 ... Oxide film, 6A ... Source electrode, 6B ... Drain electrode, 8 ... Silicon nitride film, 9 ... Photosensitive film 10 ... Polysilicon film, 10A ... Polysilicon pad

フロントページの続き (72)発明者 ドン ヤール キュム 大韓民国 キュンサンブクド チュンドク ン リ−セオミュン シンチョン 2−ド ン 462Front Page Continuation (72) Inventor Don Yar Kyum Republic of Korea Kyun Sang Buk De Chun Do Kun Lee Seomyun Sinchon 2-Dong 462

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子の製造工程にて微細コンタク
トホールを形成する方法であって、 半導体基板のコンタクト領域を含む表面に酸化膜を蒸着
する工程、 該酸化膜より蝕刻率が小さい絶縁膜を同酸化膜の表面に
蒸着する工程、 前記絶縁膜の表面に感光膜を塗布した後、マスキング工
程にて所望のパターンを形成して前記酸化膜の一部を蝕
刻により除去する工程、 前記酸化膜上に残存している前記感光膜を除去する工
程、 蝕刻によりその一部を除去した前記酸化膜と絶縁膜の表
面に所定の厚さでポリシリコン膜を蒸着する工程、 別途のマスクを使用せず、前記酸化膜が露出するよう前
記ポリシリコン膜を非等方性蝕刻することにより、前記
絶縁膜の側壁にポリシリコンパッドを形成する工程、及
び前記絶縁膜とポリシリコンパッドを蝕刻バリアとして
利用して、前記コンタクトホール領域の酸化膜を蝕刻し
てコンタクトホールを形成する工程から成ることを特徴
とする半導体素子の微細コンタクトホール形成方法。
1. A method of forming a fine contact hole in a manufacturing process of a semiconductor device, comprising a step of depositing an oxide film on a surface of a semiconductor substrate including a contact region, and an insulating film having an etching rate smaller than that of the oxide film. A step of depositing on the surface of the oxide film; a step of applying a photosensitive film on the surface of the insulating film, and then forming a desired pattern in a masking step to remove a part of the oxide film by etching; A step of removing the photoresist film remaining on the surface, a step of vapor-depositing a polysilicon film with a predetermined thickness on the surfaces of the oxide film and the insulating film, a part of which has been removed by etching, using a separate mask. First, a step of forming a polysilicon pad on the sidewall of the insulating film by anisotropically etching the polysilicon film to expose the oxide film, and etching the insulating film and the polysilicon pad A method of forming a fine contact hole in a semiconductor device, comprising the step of etching the oxide film in the contact hole region to form a contact hole by using it as a barrier.
【請求項2】 前記絶縁膜がシリコン窒化膜であること
を特徴とする請求項1に記載した半導体素子の微細コン
タクトホール形成方法。
2. The method for forming a fine contact hole in a semiconductor device according to claim 1, wherein the insulating film is a silicon nitride film.
【請求項3】 前記酸化膜を二層に蒸着するようにした
請求項1に記載した半導体素子の微細コンタクトホール
形成方法。
3. The method for forming a fine contact hole of a semiconductor device according to claim 1, wherein the oxide film is deposited in two layers.
JP5249431A 1992-10-06 1993-10-05 Method for forming fine contact hole in semiconductor device Expired - Fee Related JP2577864B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1019920018285A KR950010852B1 (en) 1992-10-06 1992-10-06 Fine contact patterning method of semiconductor device
KR92018850A KR970008353B1 (en) 1992-10-13 1992-10-13 Micro-contact formation of vlsi semiconductor elements
KR1992-18850 1992-10-13
KR1992-18285 1992-10-13

Publications (2)

Publication Number Publication Date
JPH06244129A true JPH06244129A (en) 1994-09-02
JP2577864B2 JP2577864B2 (en) 1997-02-05

Family

ID=26629289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5249431A Expired - Fee Related JP2577864B2 (en) 1992-10-06 1993-10-05 Method for forming fine contact hole in semiconductor device

Country Status (1)

Country Link
JP (1) JP2577864B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160653A (en) * 1984-02-01 1985-08-22 Hitachi Ltd Manufacture of semiconductor device
JPH03178129A (en) * 1989-12-06 1991-08-02 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPH045823A (en) * 1990-03-23 1992-01-09 Toshiba Corp Semiconductor device and its manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160653A (en) * 1984-02-01 1985-08-22 Hitachi Ltd Manufacture of semiconductor device
JPH03178129A (en) * 1989-12-06 1991-08-02 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPH045823A (en) * 1990-03-23 1992-01-09 Toshiba Corp Semiconductor device and its manufacture

Also Published As

Publication number Publication date
JP2577864B2 (en) 1997-02-05

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