KR940001285A - Contact manufacturing method of semiconductor device - Google Patents

Contact manufacturing method of semiconductor device Download PDF

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Publication number
KR940001285A
KR940001285A KR1019920011259A KR920011259A KR940001285A KR 940001285 A KR940001285 A KR 940001285A KR 1019920011259 A KR1019920011259 A KR 1019920011259A KR 920011259 A KR920011259 A KR 920011259A KR 940001285 A KR940001285 A KR 940001285A
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KR
South Korea
Prior art keywords
polysilicon
forming
bit line
mask
insulating layer
Prior art date
Application number
KR1019920011259A
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Korean (ko)
Other versions
KR100263764B1 (en
Inventor
이헌철
이호석
김일욱
박해성
Original Assignee
김주용
현대전자산업주식회사
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Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019920011259A priority Critical patent/KR100263764B1/en
Publication of KR940001285A publication Critical patent/KR940001285A/en
Application granted granted Critical
Publication of KR100263764B1 publication Critical patent/KR100263764B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

실리콘기판상에 워드라인을 형성한 후, 그 상부에 비트라인을 형성할 때 PEB(Poly Etch Back) 비트라인 및 아일랜드형 폴리실리콘을 이용하며, 저장노드 콘택시에 폴리실리콘 스페이서 자기정렬방식을 이용함으로써 식각시의 절연층 두께를 줄일 수 있다.After forming the word line on the silicon substrate, the polyetch back (PEB) bit line and island type polysilicon are used to form the bit line on the silicon substrate, and the polysilicon spacer self-aligning method is used for the storage node contact As a result, the thickness of the insulating layer during etching can be reduced.

Description

반도체소자의 콘택제조방법Contact manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 실리콘기판 상부에 워드라인을 형성하는 단계를 나타내는 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device showing a step of forming a word line on a silicon substrate.

제2도는 산화막을 식각하여 비트라인 콘택을 형성하고, 그 상부에 폴리실리콘을 증착한 후 비트라인을 형성하는 단계를 나타내는 반도체소자의 단면도.FIG. 2 is a cross-sectional view of a semiconductor device illustrating etching a oxide film to form a bit line contact, depositing polysilicon thereon, and then forming a bit line.

제3도는 폴리실리콘 스페이서를 마스크로 하여 하부의 절연막을 식각하여 저장노드 콘택홀을 형성하는 단계를 나타내는 반도체소자의 단면도.3 is a cross-sectional view of a semiconductor device illustrating a step of forming a storage node contact hole by etching a lower insulating film using a polysilicon spacer as a mask.

Claims (1)

반도체소자의 콘택을 형성하는 방법에 있어서, 실리콘기판(1)을 제공하는 단계와, 상기 실리콘기판(1) 소정부분에 필드 산화막(3)을 형성하는 단계와, 전체구조 상부에 폴리실리콘층(5), 절연막(7), 아일랜드형 박막 폴리실리콘층(9)을 형성하는 단계와, 상기 아일랜드형 박막 폴리실리콘(9) 상부에 절연층을 형성하고 마스크공정후, 하부의 아일랜드형 박막 폴리실리콘층(9), 절연막(7) 및 폴리실리콘(5)을 순차적으로 식각하여, 워드라인을 형성하고, 측벽에 스페이서(11)를 형성하는 단계와, 상기 워드라인 상부로부터 절연막(7)을 증착한 후, 마스크 공정 후, 아일랜드형 박막 폴리실리콘(9)을 베리어로 절연막(7)의 소정부분을 식각하여, 비트라인 콘택(15)을 형성하는 단계와, 상기 비트라인 콘택(15)내에 폴리실리콘을 충진시키고, 그 상부에 비트라인(17)을 형성하는 단계와, 상기 비트라인(17) 상부에 절연층(19)을 증착시켜 평탄화된 구조를 형성하는 단계와, 상기 절연층(19) 상부에 마스크 폴리실리콘을 증착하고, 마스크공정을 이용하여 상기 마스크 폴리실리콘 및 절연막 소정부분을 식각하고, 그 상부에 다시 폴리실리콘을 증착한 후, 식각하여 스페이서 폴리실리콘(18)을 형성하는 단계와, 상기 스페이서 폴리실리콘(18) 및 마스크 폴리실리콘(21)을 이용하여 하부의 절연막(19)을 식각하여, 저장노드용 콘택(23)을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.A method of forming a contact of a semiconductor device, comprising: providing a silicon substrate 1, forming a field oxide film 3 on a predetermined portion of the silicon substrate 1, and forming a polysilicon layer on the entire structure ( 5) forming an insulating layer 7 and an island type thin film polysilicon layer 9, forming an insulating layer on the island type thin film polysilicon 9, and masking the island type thin film polysilicon Sequentially etching the layer 9, the insulating film 7 and the polysilicon 5 to form a word line, forming a spacer 11 on the sidewalls, and depositing the insulating film 7 from above the word line. After the mask process, a predetermined portion of the insulating film 7 is etched using the island-type thin-film polysilicon 9 as a barrier to form a bit line contact 15, and the poly within the bit line contact 15. Fill the silicon, and form the bit line 17 on top And depositing an insulating layer 19 on the bit line 17 to form a planarized structure, depositing mask polysilicon on the insulating layer 19, and using a mask process. Etching the mask polysilicon and a predetermined portion of the insulating film, depositing polysilicon on the upper portion of the mask polysilicon and the insulating layer, and then etching to form the spacer polysilicon 18; the spacer polysilicon 18 and the mask polysilicon 21; Etching the lower insulating film (19) to form a contact for the storage node (23). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920011259A 1992-06-26 1992-06-26 Method of forming contact in semiconductor device KR100263764B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920011259A KR100263764B1 (en) 1992-06-26 1992-06-26 Method of forming contact in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920011259A KR100263764B1 (en) 1992-06-26 1992-06-26 Method of forming contact in semiconductor device

Publications (2)

Publication Number Publication Date
KR940001285A true KR940001285A (en) 1994-01-11
KR100263764B1 KR100263764B1 (en) 2000-09-01

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KR1019920011259A KR100263764B1 (en) 1992-06-26 1992-06-26 Method of forming contact in semiconductor device

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KR100263764B1 (en) 2000-09-01

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