KR940001285A - Contact manufacturing method of semiconductor device - Google Patents
Contact manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR940001285A KR940001285A KR1019920011259A KR920011259A KR940001285A KR 940001285 A KR940001285 A KR 940001285A KR 1019920011259 A KR1019920011259 A KR 1019920011259A KR 920011259 A KR920011259 A KR 920011259A KR 940001285 A KR940001285 A KR 940001285A
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- forming
- bit line
- mask
- insulating layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000003860 storage Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims abstract 4
- 238000000151 deposition Methods 0.000 claims description 5
- 239000010408 film Substances 0.000 claims 6
- 239000010409 thin film Substances 0.000 claims 4
- 230000004888 barrier function Effects 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
실리콘기판상에 워드라인을 형성한 후, 그 상부에 비트라인을 형성할 때 PEB(Poly Etch Back) 비트라인 및 아일랜드형 폴리실리콘을 이용하며, 저장노드 콘택시에 폴리실리콘 스페이서 자기정렬방식을 이용함으로써 식각시의 절연층 두께를 줄일 수 있다.After forming the word line on the silicon substrate, the polyetch back (PEB) bit line and island type polysilicon are used to form the bit line on the silicon substrate, and the polysilicon spacer self-aligning method is used for the storage node contact As a result, the thickness of the insulating layer during etching can be reduced.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 실리콘기판 상부에 워드라인을 형성하는 단계를 나타내는 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device showing a step of forming a word line on a silicon substrate.
제2도는 산화막을 식각하여 비트라인 콘택을 형성하고, 그 상부에 폴리실리콘을 증착한 후 비트라인을 형성하는 단계를 나타내는 반도체소자의 단면도.FIG. 2 is a cross-sectional view of a semiconductor device illustrating etching a oxide film to form a bit line contact, depositing polysilicon thereon, and then forming a bit line.
제3도는 폴리실리콘 스페이서를 마스크로 하여 하부의 절연막을 식각하여 저장노드 콘택홀을 형성하는 단계를 나타내는 반도체소자의 단면도.3 is a cross-sectional view of a semiconductor device illustrating a step of forming a storage node contact hole by etching a lower insulating film using a polysilicon spacer as a mask.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920011259A KR100263764B1 (en) | 1992-06-26 | 1992-06-26 | Method of forming contact in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920011259A KR100263764B1 (en) | 1992-06-26 | 1992-06-26 | Method of forming contact in semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940001285A true KR940001285A (en) | 1994-01-11 |
KR100263764B1 KR100263764B1 (en) | 2000-09-01 |
Family
ID=19335343
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920011259A KR100263764B1 (en) | 1992-06-26 | 1992-06-26 | Method of forming contact in semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100263764B1 (en) |
-
1992
- 1992-06-26 KR KR1019920011259A patent/KR100263764B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100263764B1 (en) | 2000-09-01 |
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A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
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FPAY | Annual fee payment |
Payment date: 20080425 Year of fee payment: 9 |
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