KR940016577A - Vertical Storage Node Formation Method for Semiconductor Devices - Google Patents

Vertical Storage Node Formation Method for Semiconductor Devices Download PDF

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Publication number
KR940016577A
KR940016577A KR1019920026868A KR920026868A KR940016577A KR 940016577 A KR940016577 A KR 940016577A KR 1019920026868 A KR1019920026868 A KR 1019920026868A KR 920026868 A KR920026868 A KR 920026868A KR 940016577 A KR940016577 A KR 940016577A
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South Korea
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film
forming
storage node
oxide film
photoresist
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KR1019920026868A
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Korean (ko)
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KR960003758B1 (en
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김영서
박상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019920026868A priority Critical patent/KR960003758B1/en
Publication of KR940016577A publication Critical patent/KR940016577A/en
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Publication of KR960003758B1 publication Critical patent/KR960003758B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor

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  • Semiconductor Memories (AREA)

Abstract

본 발명은 이중 감광막 공정을 이용하여 측면 산화막의 높이 차이에 관계없이, 일정한 형태의 수직 스토리지 노드를 형성하는 방법으로서, 반도체 기판(11)위에 필드 산화막(12) 및 게이트 전극(13)과 스페이서용 측면 산화막(14)을 형성한 다음에, N+확산층(15)을 형성하고, 절연용 산화막(16)을 증착하고 나서 사진 식각법으로 소정 부분을 오픈하는 제 1 단계와, 제 1 폴리실리콘막(17)을 증착하고, 그 위에 제 1 감광막(18)을 소정의 두께로 도포한 다음에, 제 1 감광막(18)의 패턴을 형성한 후, 식각에 의해 제 1 폴리실리콘막(17)의 소정 부위를 제거하는 제 2 단계와, 잔류되어 있은 제 1 감광막(18)을 제거하지 않은 상태에서, 제 2 감광막(19)을 도포한 다음에 수직 스토리지 노드가 형성될 일정한 패턴을 형성하여 식각하는 제 3 단계와, 평탄화를 위한 산화막(20)을 증착하는 제 4 단계와, 제 2 감광막(19)이 드러날때까지 TEOS-Ozone 막(20)을 식각한 다음에, 상기 제1 및 제 2 감광막(18, 19)을 제거하고, 제 2 폴리실리콘(21)을 증착한 후, 사진 식각에 의해 수직 형태의 스토리지 노드를 형성하는 제 5 단계를 포함하고 있다.The present invention is a method of forming a vertical storage node of a certain shape regardless of the height difference of the side oxide film using a double photoresist film process, for the field oxide film 12, the gate electrode 13 and the spacer on the semiconductor substrate 11 After forming the side oxide film 14, the first step of forming the N + diffusion layer 15, depositing the insulating oxide film 16, and then opening a predetermined portion by photolithography, and the first polysilicon film (17) is deposited, the first photoresist film 18 is applied thereon to a predetermined thickness, and then a pattern of the first photoresist film 18 is formed, followed by etching of the first polysilicon film 17. After the second step of removing the predetermined portion and the remaining first photoresist film 18 are not removed, the second photoresist film 19 is applied and then a predetermined pattern for forming a vertical storage node is formed to be etched. And the oxide film 20 for planarization After etching the TEOS-Ozone film 20 until the fourth step and the second photoresist film 19 are exposed, the first and second photoresist films 18 and 19 are removed, and the second polysilicon is removed. After depositing 21, a fifth step of forming a storage node in a vertical form by photolithography is included.

Description

반도체 소자의 수직 스토리지 노드 형성 방법Vertical Storage Node Formation Method for Semiconductor Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 종래의 수직 스토리지 노드 형성 방법의 공정도, 제 2 도는 본 발명에 따른 수직 스토리지 노드 형성 방법의 공정도.1 is a process diagram of a conventional vertical storage node forming method, and FIG. 2 is a process diagram of a vertical storage node forming method according to the present invention.

Claims (2)

반도체 소자의 수직 스토리지 노드를 형성하는 방법에 있어서, 반도체 기판(11)위에 필드 산화막(12)및 게이트 전극(13)과 스페이서용 측면 산화막(14)을 형성한 다음에, N+확산층(15)을 형성하고, 절연용 산화막(16)을 증착하고 나서 사진 식각법으로 소정부분을 오픈하는 제 1 단계와, 제 1 폴리실리콘막(17)을 증착하고, 그 위에 제 1 감광막(18)을 소정의 두께로 도포한 다음에, 제 1 감광막(18)의 패턴을 형성한 후, 식각에 의해 제 1 폴리실리콘막(17)의 소정 부위를 제거하는 제 2 단계와, 잔류되어 있는 제 1 감광막(18)을 제거하지 않은 상태에서, 제 2 감광막(19)을 도포한 다음에 수직 스토리지 노드가 형성될 일정한 패턴을 형성하여 식각하는 제 3 단계와, 평탄화를 위한 산화막(20)을 증착하는 제 4 단계와, 제 2 감광막(19)이 드러날 때까지 TEOS-Ozone막(20)을 식각한 다음에, 상기 제1 및 제 2 감광막(18, 19)을 제거하고, 제 2 폴리실리콘(21)을 증착한 후, 사진 식각에 의해 수직 형태의 스토리지 노드를 형성하는 제 5 단계를 포함하는 것을 특징으로 하는 반도체 소자의 스토리지 노드 형성 방법.In the method for forming a vertical storage node of a semiconductor device, after forming the field oxide film 12 and the gate electrode 13 and the spacer side oxide film 14 on the semiconductor substrate 11, the N + diffusion layer 15 is formed. The first step of opening the predetermined portion by photolithography after depositing the insulating oxide film 16, and depositing the first polysilicon film 17, the first photosensitive film 18 is deposited thereon. After coating to a thickness of, the pattern of the first photosensitive film 18 is formed, and then a second step of removing a predetermined portion of the first polysilicon film 17 by etching, and the remaining first photosensitive film ( 18), the third step of applying a second photoresist film 19 and then forming and etching a predetermined pattern in which the vertical storage node is to be formed, and the fourth step of depositing the oxide film 20 for planarization. And etching the TEOS-Ozone film 20 until the second photoresist film 19 is exposed. Next, a fifth step of removing the first and second photoresist layers 18 and 19, depositing the second polysilicon 21, and forming a storage node having a vertical shape by photolithography is performed. A method for forming a storage node of a semiconductor device. 제 1 항에 있어서, 평탄화용 산화막(20)은 TEOS-Ozone막 또는 저온 산화막중 어느 하나인 것을 특징으로 하는 반도체 소자의 수직 스토리지 노드 형성 방법.The method of claim 1, wherein the planarization oxide film is one of a TEOS-Ozone film and a low temperature oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920026868A 1992-12-30 1992-12-30 Forming method of vertical storage node for semiconductor device KR960003758B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920026868A KR960003758B1 (en) 1992-12-30 1992-12-30 Forming method of vertical storage node for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920026868A KR960003758B1 (en) 1992-12-30 1992-12-30 Forming method of vertical storage node for semiconductor device

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KR940016577A true KR940016577A (en) 1994-07-23
KR960003758B1 KR960003758B1 (en) 1996-03-22

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