KR960010054B1 - Contact forming method of semiconductor device - Google Patents

Contact forming method of semiconductor device Download PDF

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Publication number
KR960010054B1
KR960010054B1 KR1019920023775A KR920023775A KR960010054B1 KR 960010054 B1 KR960010054 B1 KR 960010054B1 KR 1019920023775 A KR1019920023775 A KR 1019920023775A KR 920023775 A KR920023775 A KR 920023775A KR 960010054 B1 KR960010054 B1 KR 960010054B1
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South Korea
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insulating layer
photoresist
pattern
layer
etching
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KR1019920023775A
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Korean (ko)
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KR940016439A (en
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김명선
김진웅
복철규
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현대전자산업 주식회사
김주용
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Priority to KR1019920023775A priority Critical patent/KR960010054B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

forming a micro photoresist pattern (9A) on a second insulating layer (8) including the region where a contact is formed; depositing a photoresist thinner than the second insulating layer pattern (8A) after patterning the second insulating layer (8) by etching and removing the above photoresist pattern; forming a micro contact hole (11) by etching the revealed second insulating layer pattern (8A), an etching barrier (7) and a first insulating layer (6) to reveal the contact region.

Description

반도체소자의 콘택형성방법Contact Forming Method of Semiconductor Device

제1도 내지 제3도는 본 발명에 의해 미세콘택홀 형성단계를 도시한 단면도.1 to 3 are cross-sectional views showing a micro contact hole forming step according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판2 : 필드 산화막1 silicon substrate 2 field oxide film

3 : 게이트 산화막4 : 게이트폴리3: gate oxide film 4: gate poly

5 : 스페이서 절연막6 : 제1절연층5: spacer insulating film 6: first insulating layer

7 : 식각베리어층8 : 제2절연층7: etching barrier layer 8: second insulating layer

9 : 네가티브감광막9A : 네가티브감광막 패턴9: negative photoresist 9A: negative photoresist pattern

10 : 감광막11 : 미세콘택홀10 photosensitive film 11: fine contact hole

본 발명은 고집적 반도체소자의 미세한 콘택홀 형성방법에 관한 것으로, 특히 단일 감광막을 이용하여 예정된 콘택영역에 서브-하프 마이크론(Sub-half micron)감광막 패턴을 형성한 후, 후속공정에 의해 미세한 콘택홀을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact hole in a highly integrated semiconductor device. In particular, after forming a sub-half micron photoresist pattern in a predetermined contact region using a single photoresist layer, a fine contact hole is formed by a subsequent process. It relates to a method of forming a.

종래의 기술은 단일 감광막을 이용하여 서브-하프 마이크론급 콘택홀 패턴을 형성하는 것은 어려움이 있다. 왜냐하면 리소그라피(Lithography) 공정시 라인을 형성할 때 노광조건을 조절하여 선폭 크기(Critical Dimension)을 조절할 수 있으나, 콘택홀에서는 콘택홀의 크기를 줄이는데 한계가 있다. 이에 따라 삼층 감광막 패턴 형성방법과 실리레이션 감광막 패턴 형성방법을 이용하여 미세 콘택홀을 형성하게 되었다.The prior art has a difficulty in forming a sub-half micron contact hole pattern using a single photoresist film. This is because, in the lithography process, when the line is formed, the exposure conditions may be adjusted to control the line dimensions, but there is a limit in reducing the size of the contact hole in the contact hole. Accordingly, the fine contact hole was formed by using the three-layer photoresist pattern forming method and the siliculation photoresist pattern forming method.

그러나, 삼층 감광막 또는 실리레이션 감광막 패턴 형성방법은 복잡한 공정을 거쳐야하므로 생산성이 떨어지는 단점이 있다.However, the three-layer photosensitive film or the silicidation photosensitive film pattern forming method has a disadvantage in that productivity is poor because it must go through a complicated process.

따라서 본 발명은 단일 감광막을 이용하면서 비교적 간단한 공정으로 미세 콘택홀을 형성할 수 있는 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a fine contact hole in a relatively simple process using a single photosensitive film.

본 발명에 의하면, 단일 감광막으로 네가티브 감광막을 사용하거나 포지티브 감광막을 사용하되 리버스 마스크(Reverse Mask)를 사용하여 예정된 콘택홀 상부에만 감광막이 남은 감광막 패턴을 형성하고, 이 감광막 패턴을 마스크로 사용하여 하부에 절연층패턴을 형성하고 감광막 패턴을 제거한 후, 다시 감광막을 절연층 패턴보다 낮은 두께로 도포하고, 이 감광막을 마스크로 하여 노출된 절연층 패턴과 그 하부의 층들을 식각하여 미세한 콘택홀을 형성하는 것을 특징으로 한다.According to the present invention, a negative photoresist film or a positive photoresist film is used as a single photoresist film, but a reverse photoresist film is used to form a photoresist pattern in which a photoresist film remains only on a predetermined contact hole, and the photoresist pattern is used as a mask. After forming the insulating layer pattern on the substrate and removing the photoresist pattern, the photoresist is applied to a thickness lower than that of the insulating layer pattern, and the exposed insulating layer pattern and the layers below it are etched using the photoresist as a mask to form fine contact holes Characterized in that.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제1도는 실리콘 기판(1)의 소정부분에 필드산화막(2)을 형성하고, 게이트 산화막(3), 게이트폴리(4) 및 스페이서 절연막(5)들을 형성한 후, 전체구조 상부에 층간절연층용 제1절연층(6)과 상부에 형성되는 제2절연층 식각시 베리어층으로 사용되는 식각베리어층(7) 예를 들어 폴리실리콘층을 형성하고, 그 상부에 제2절연층(8)을 적층한 다음, 제2절연층(8) 상부에 네가티브 감광막(9)을 도포한 다음, 콘택마스크를 이용한 노광 및 현상공정으로 예정된 콘택홀 영역에만 감광막을 남긴 감광막 패턴(9A)을 형성한 단면도이다. 상기 네가 티브 감광막 대신에 포지티브 감광막을 사용하되 리버스마스크를 사용하면 예정된 콘택영역에만 감광막패턴을 형성할 수 있다.1 shows the field oxide film 2 formed on a predetermined portion of the silicon substrate 1, the gate oxide film 3, the gate poly 4 and the spacer insulating films 5 are formed, and then the interlayer insulating layer is formed on the entire structure. An etching barrier layer 7 used as a barrier layer for etching the first insulating layer 6 and the second insulating layer formed thereon, for example, a polysilicon layer is formed, and a second insulating layer 8 is formed thereon. After the lamination, the negative photoresist film 9 is applied on the second insulating layer 8, and then the photoresist pattern 9A is formed in which the photoresist film is left only in the contact hole region intended for the exposure and development process using a contact mask. . If a positive photoresist film is used instead of the negative photoresist film but a reverse mask is used, the photoresist pattern may be formed only in a predetermined contact region.

제2도는 상기 감광막패턴(9A)을 마스크로 하고 노출된 제2절연층(8)을 식각하여 제2절연층 패턴(8A)을 형성하고, 상기 감광막 패턴(9A)을 제거한 후, 포지티브 또는 네가티브 감광막(10)을 상기 제2절연층 패턴(8A)의 두께보다 낮은 두께로 코팅한 상태의 단면도이다.2 shows the second insulating layer 8 by using the photoresist pattern 9A as a mask and etching the exposed second insulating layer 8 to form the second insulating layer pattern 8A. After removing the photoresist pattern 9A, the positive or negative It is sectional drawing of the photosensitive film 10 coated with thickness lower than the thickness of the said 2nd insulating layer pattern 8A.

제3도는 제2도 공정 후 감광막(10)을 마스크로 하고 노출된 제2절연층 패턴(8A)을 제거하고, 계속하여 노출되는 식각베리어층(7)과 제1절연층(6)을 식각하여 실리콘기판(1)이 노출되는 미세콘택홀(11)을 형성한 단면도이다.3 shows the photoresist layer 10 as a mask after the process of FIG. 2, removing the exposed second insulating layer pattern 8A, and subsequently etching the etch barrier layer 7 and the first insulating layer 6 that are subsequently exposed. 3 is a cross-sectional view of the micro contact hole 11 exposing the silicon substrate 1.

상기한 본 발명에 의하면 미세한 크기를 갖는 감광막 패턴을 형성한 후, 이 감광막 패턴을 콘택홀에 전사시켜 동일한 크기로 콘택홀을 형성할 수가 있으므로 삼층감광막이나 실리레이션 감광막을 이용하지 않고도 미세한 콘택홀을 형성할 수가 있다.According to the present invention described above, after forming a photoresist pattern having a fine size, the photoresist pattern can be transferred to the contact hole to form a contact hole with the same size. Thus, a fine contact hole can be formed without using a three-layer photoresist film or a silicide photoresist film. It can be formed.

Claims (2)

반도체소자의 미세콘택홀 제조방법에 있어서, 제1절연층 상부에 식각베리어층과 제2절연층을 각각 예정된 두께로 적층한 다음, 제2절연층 상부에 감광막 패턴을 형성하되, 예정된 콘택영역에 감광막이 남은 미세한 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 하여 노출된 제2절연층을 식각하여 제2절연층 패턴을 형성하고 상기 감광막 패턴을 제거한 후, 다시 감광막을 도포하되 제2절연층 패턴을 두께보다 낮은 두께로 도포하는 단계와, 노출된 제2절연층 패턴을 식각하고, 계속하여 식각베리어층과 제1절연층을 식각하여 식각베어링층과 제1절연층을 식각하여 예정된 콘택영역이 노출된 미세콘택홀을 형성하는 단계를 포함하는 반도체소자의 미세콘택홀 형성방법.In the method for manufacturing a micro contact hole of a semiconductor device, an etch barrier layer and a second insulating layer are laminated on the first insulating layer to a predetermined thickness, and a photoresist pattern is formed on the second insulating layer, Forming a fine photoresist pattern left over by the photoresist layer, etching the exposed second insulation layer using the photoresist pattern as a mask to form a second insulation layer pattern, removing the photoresist pattern, and then applying a photoresist layer again Coating the insulating layer pattern to a thickness lower than the thickness, etching the exposed second insulating layer pattern, and subsequently etching the etch barrier layer and the first insulating layer to etch the etching bearing layer and the first insulating layer. Forming a micro contact hole exposing a contact region; 제1항에 있어서, 상기 제2절연층 상부에 형성되는 감광막 패턴은 네가티브 감광막을 도포한 후 콘택마스크를 사용한 노광 및 현상공정으로 형성하는 것을 특징으로 하는 반도체소자의 미세콘택홀 형성방법.The method of claim 1, wherein the photoresist pattern formed on the second insulating layer is formed by exposure and development using a contact mask after applying a negative photoresist.
KR1019920023775A 1992-12-10 1992-12-10 Contact forming method of semiconductor device KR960010054B1 (en)

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KR960010054B1 true KR960010054B1 (en) 1996-07-25

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