KR960000232B1 - Making method of gate pattern for semiconductor device - Google Patents
Making method of gate pattern for semiconductor device Download PDFInfo
- Publication number
- KR960000232B1 KR960000232B1 KR1019920026722A KR920026722A KR960000232B1 KR 960000232 B1 KR960000232 B1 KR 960000232B1 KR 1019920026722 A KR1019920026722 A KR 1019920026722A KR 920026722 A KR920026722 A KR 920026722A KR 960000232 B1 KR960000232 B1 KR 960000232B1
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- South Korea
- Prior art keywords
- pattern
- film
- gate
- semiconductor device
- oxide film
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 238000010030 laminating Methods 0.000 claims abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
제1a도 내지 제1d도는 종래의 기술방법에 의하여 패턴을 형성한 단면도.1A to 1D are cross-sectional views in which a pattern is formed by a conventional technical method.
제2a도 내지 제2d도는 본 발명에 의한 패턴 형성단계를 나타낸 단면도.2a to 2d is a cross-sectional view showing a pattern forming step according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 필드산화막1: silicon substrate 2: field oxide film
3 : 게이트 산화막 4 : 게이트 폴리실리콘3: gate oxide film 4: gate polysilicon
5 : 포지티브 감광막 6 : 게이트전극 마스크5 positive photosensitive film 6 gate electrode mask
7 : 입사광 8 : 반사광7: incident light 8: reflected light
9 : 감광막패턴 10 : 게이트전극9: photosensitive film pattern 10: gate electrode
11 : 산화막 12 : 네가티브 감광막11: oxide film 12: negative photosensitive film
본 발명은 반도체 소자의 게이트패턴 형성방법에 관한 것으로 특히 감광막을 도포하여 패턴을 형성할 때 네기티브 감광막과 산화막을 마스크로 사용하여 패턴의 노팅(notching) 현상을 방지하는 반도체 소자의 게이트패턴 형성방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate pattern of a semiconductor device. In particular, when forming a pattern by applying a photosensitive film, a method of forming a gate pattern of a semiconductor device using a negative photosensitive film and an oxide film as a mask to prevent notching of the pattern. to be.
도면 제1a도 내지 제1d도를 참조하여 종래기술에 의해 패턴을 형성하는 방법을 설명해보면, 제1a도는 실리콘기판(1) 상부에 소자의 분리를 위한 필드산화막(2)을 형성하고 그 상부에 게이트산화막(3)과 게이트 폴리실리콘(4)을 적층한 후 포지티브 감광막(5)을 도포한 단면도이며, 감광막의 두께는 보통 1㎛ 이상의 두께로 도포하게 된다.Referring to FIGS. 1A to 1D, a method of forming a pattern according to the related art will be described. Referring to FIG. 1A, a field oxide film 2 is formed on an upper surface of a silicon substrate 1 to separate a device. After the gate oxide film 3 and the gate polysilicon 4 are laminated, the positive photoresist film 5 is coated, and the thickness of the photoresist film is usually applied to a thickness of 1 μm or more.
제1b도는 포지티브 감광막(5) 상에 게이트 전극마스크(6)를 씌우고 노광시켰을 때 입사광(7) 및 반사광(8) 경로를 나타낸 단면도이며 노광시 필드산화막(2)의 경사진 면으로부터 반사되어 나온 빛이 게이트전극 마스크(6)로 씌워진 감광막의 아래부분을 노광시키게 된다.FIG. 1B is a cross-sectional view showing the incident light 7 and the reflected light 8 paths when the gate electrode mask 6 is exposed on the positive photoresist film 5 and exposed from the inclined surface of the field oxide film 2 during exposure. Light exposes the lower portion of the photosensitive film covered with the gate electrode mask 6.
제1c도는 현상용액에 현상시켰을 때 입사광 및 반사광으로 노광된 포지티브 감광막(5)은 용해되어 없어지고 노광되지 않은 감광막만 남아 감광막 패턴(9)을 형성한 단면도이며 감광막패턴(9)의 아래부분에 노칭이 발생한 것을 알 수 있다.1C is a cross-sectional view in which the positive photoresist film 5 exposed to incident light and reflected light when dissolved in a developing solution is dissolved and disappears and only the unexposed photoresist film remains to form the photoresist pattern 9. It can be seen that notching has occurred.
제1d도는 감광막 패턴(9)을 마스크로 하여 게이트폴리실리콘(4)을 식각한 다음 감광막 패턴(9)을 제거한 것으로서 게이트전극(10)이 형성된 단면도이며 제1c도에서의 감광막 패턴(9)과 같이 게이트전극(10)의 아래부분의 넓이가 작아져 게이트 전극의 특성에 나쁜 영향을 주게 된다.FIG. 1D is a cross-sectional view in which the gate polysilicon 4 is etched using the photoresist pattern 9 as a mask and then the photoresist pattern 9 is removed to form a gate electrode 10. The photoresist pattern 9 and the photoresist pattern 9 of FIG. Likewise, the width of the lower portion of the gate electrode 10 is reduced, which adversely affects the characteristics of the gate electrode.
또한 종래방법에서는 게이트폴리실리콘 식각에 대한 마스크 역할을 충분히 하기 위하여 감광막의 두께를 통상 1㎛ 이상으로 도포하며 감광막의 두께가 두꺼워지며 잠재이미지(Latent Image)의 광콘트라스트가 저하되기 때문에 해상도가 감소하게 된다.In addition, in the conventional method, the thickness of the photoresist film is generally applied to 1 μm or more in order to sufficiently serve as a mask for gate polysilicon etching, and the thickness of the photoresist film is increased and the light contrast of the latent image is reduced, thereby reducing the resolution. do.
따라서 본 발명에서는 게이트전극마스크를 통고한 빛이 필드산화막의 경사진면에 도달되지 않도록 하기 위하여 마스크 폴라리티(Mask Polarity)를 종래방법과 반대로 하고 네가티브 감광막을 사용하여 노칭현상을 방지하며 산화막을 마스크로 사용하여 감광막의 두께를 감소시키는 반도체 소자의 게이트패턴 형성방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, in order to prevent the light passing through the gate electrode mask from reaching the inclined surface of the field oxide film, mask polarity is reversed from the conventional method, and a negative photosensitive film is used to prevent notching and mask the oxide film. It is an object of the present invention to provide a method for forming a gate pattern of a semiconductor device to reduce the thickness of the photoresist film.
이하 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
제2a도는 실리콘 기판(1) 상부에 소자분리를 위한 필드산화막(2)을 형성한 후 게이트산화막(3)과 게이트 폴리실리콘(4)을 적층한 다음 게이트폴리실리콘에 대한 식각마스크로서 산화막(11)과 네가티브감광막(12)을 도포한 단면도로서 네가티브감광막(12)은 0.5㎛ 정도의 두께로 도포한다.FIG. 2A illustrates the formation of the field oxide film 2 for device isolation on the silicon substrate 1, stacking the gate oxide film 3 and the gate polysilicon 4, and then forming the oxide film 11 as an etching mask for the gate polysilicon. ) And the negative photosensitive film 12 is a cross-sectional view, the negative photosensitive film 12 is applied to a thickness of about 0.5㎛.
제2b도는 네가티브 감광막(5)상에 게이트 전극마스크(6)을 씌우고 노광시켰을 때 입사광(7) 및 반사광(8)의 경로를 나타낸 단면도이며 입사경로와 반사경로가 동일함을 나타낸다.FIG. 2B is a cross-sectional view showing the paths of the incident light 7 and the reflected light 8 when the gate electrode mask 6 is exposed on the negative photosensitive film 5, and shows that the incident path and the reflective path are the same.
제2c도는 현상시켰을 때 입사광(7) 및 반사광(8)으로 노광되지 않은 지역은 현상액에 용해되어 없어지고 노광된 지역은 패턴으로 남은 상태의 단면도이며, 네가티브 감광막은 비노광지역의 감광막은 현상액에 제거되고 노광지역막 패턴으로 남게 되며 노칭현상이 발생되지 않은 감광막패턴(9)이 형성됨을 알 수 있다.FIG. 2C is a cross-sectional view of the unexposed areas where the unexposed areas of the incident light 7 and the reflected light 8 are dissolved in the developing solution and the exposed areas remain in a pattern when developed. The negative photoresist film is a non-exposed area photosensitive film. It can be seen that the photoresist pattern 9, which is removed, remains as an exposure region layer pattern, and where notching occurs, is formed.
제2d도는 감광막패턴(9)을 마스크로 하여 산화막(11)을 식각한 다음 감광막패턴(10)을 제거하고 다시 산화막(11)을 마스크로 하여 게이트폴리실리콘(4)을 식각하여 게이트전극(10)을 형성한 단면도이다.2D illustrates that the oxide film 11 is etched using the photoresist pattern 9 as a mask, the photoresist pattern 10 is removed, and the gate polysilicon 4 is etched again using the oxide film 11 as a mask. ) Is a cross-sectional view.
본 발명에 의하면 네가티브감광막을 사용하여 패턴을 형성시킴으로써 빛의 반상 의한 노칭현성이 전혀 없으며 게이트폴리실리콘 식각시 미스크로서 산화막을 이용하기 때문에 감광막의 두께를 얇게하므로써 해상도를 증가시킬 수 있다.According to the present invention, since the pattern is formed using the negative photoresist film, there is no notching phenomenon due to the reflection of light at all, and since the oxide film is used as a misc for gate polysilicon etching, the resolution can be increased by thinning the photoresist film.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920026722A KR960000232B1 (en) | 1992-12-30 | 1992-12-30 | Making method of gate pattern for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920026722A KR960000232B1 (en) | 1992-12-30 | 1992-12-30 | Making method of gate pattern for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940016943A KR940016943A (en) | 1994-07-25 |
| KR960000232B1 true KR960000232B1 (en) | 1996-01-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920026722A KR960000232B1 (en) | 1992-12-30 | 1992-12-30 | Making method of gate pattern for semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR960000232B1 (en) |
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1992
- 1992-12-30 KR KR1019920026722A patent/KR960000232B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR940016943A (en) | 1994-07-25 |
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