JP2810061B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2810061B2
JP2810061B2 JP22866988A JP22866988A JP2810061B2 JP 2810061 B2 JP2810061 B2 JP 2810061B2 JP 22866988 A JP22866988 A JP 22866988A JP 22866988 A JP22866988 A JP 22866988A JP 2810061 B2 JP2810061 B2 JP 2810061B2
Authority
JP
Japan
Prior art keywords
light
phase shift
pattern
phase
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP22866988A
Other languages
Japanese (ja)
Other versions
JPH0278216A (en
Inventor
昇雄 長谷川
稔彦 田中
二三夫 村井
恒男 寺澤
紳一郎 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
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Publication of JPH0278216A publication Critical patent/JPH0278216A/en
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Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子、磁気バブル素子などの製造工程
で行なわれるリソグラフイ技術に係り、特に微細パター
ン形成を有する半導体装置の製造方法に関する。
Description: BACKGROUND OF THE INVENTION The present invention relates to a lithography technique performed in a manufacturing process of a semiconductor element, a magnetic bubble element, and the like, and more particularly, to a method of manufacturing a semiconductor device having a fine pattern.

〔従来の技術〕[Conventional technology]

半導体素子や磁気バブルの微細化、高集積化に伴なつ
て、リソグラフイ工程に用いられる投影露光装置には、
転写できるパターンの微細化、高解像度化が要求されて
いる。投影露光装置がどの程度微細なパターンまで転写
できるかを表わす解像力は、レテイクル上のパターンが
ウエーハ上に転写された時、隣接する2ケ所の明部が分
離できるかどうかで評価される。この解像力を向上させ
る一手法として、レテイクル上の隣接する2ケ所の透過
部分の露光光に位相差を与えればよいことが知られてい
る。従来、露光光に位相差を与えるレテイクルパターン
については、例えば特開昭58−173744が挙げられる。こ
の従来例では、実用に耐えうるレテイクルの構造および
その製造方法は開示されていない。また、半導体装置の
電荷蓄積キャパシタのパターン形成については特開昭59
−231851に記載されているが、位相シフトマスクを用い
たパターン形成については記載されていない。
With the miniaturization and high integration of semiconductor elements and magnetic bubbles, projection exposure equipment used in the lithography process includes:
There is a demand for miniaturization and high resolution of patterns that can be transferred. The resolution which indicates how fine a pattern can be transferred by a projection exposure apparatus is evaluated based on whether or not two adjacent bright portions can be separated when a pattern on a reticle is transferred onto a wafer. It is known that as one method of improving the resolving power, a phase difference may be given to exposure light at two adjacent transmission portions on the reticle. Conventionally, a reticle pattern for giving a phase difference to exposure light is disclosed in, for example, JP-A-58-173744. This conventional example does not disclose a reticle structure that can be put to practical use and a manufacturing method thereof. Japanese Patent Laid-Open Publication No.
-231851, but does not describe pattern formation using a phase shift mask.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上記従来技術においては、電子線露光を用いた位相シ
フトパターン描画時の帯電防止について配慮がされてお
らず、電子線描画時に被描画基板に電子が帯電し、パタ
ーン寸法の変動、パターン位置誤差の発生等が問題とな
つていた。
In the above prior art, no consideration is given to the prevention of electrification at the time of drawing a phase shift pattern using electron beam exposure.Electrons are charged on a substrate to be drawn at the time of drawing an electron beam, fluctuations in pattern dimensions, and errors in pattern position errors. Occurrence was a problem.

原画パターンの描画時にはガラス基板上全面に通常Cr
膜(遮光膜)があるため、Cr膜を通してアースされるた
め、帯電は起こらない。一方、位相シフトパターンの描
画は、ほとんどCr膜の無い透過部となるため、帯電が発
生する。
When drawing the original pattern, the entire surface of the glass substrate is usually Cr
Since there is a film (light shielding film), it is grounded through the Cr film, so that no charging occurs. On the other hand, the drawing of the phase shift pattern becomes a transmission part having almost no Cr film, so that charging occurs.

本発明の目的は、位相シフトパターン描画時に帯電が
起こらないプロセスを構築することにある。本発明の他
の目的は、半導体装置の微細な繰り返しパターンを解像
度よく形成することにある。また、本発明の他の目的
は、半導体装置の電荷蓄積キャパシタを形成するにあた
り、限られた専有面積の中で、できるだけ容量の大きい
キャパシタを形成できるような技術を提供することにあ
る。
An object of the present invention is to construct a process that does not cause charging when drawing a phase shift pattern. Another object of the present invention is to form a fine repetitive pattern of a semiconductor device with high resolution. It is another object of the present invention to provide a technique capable of forming a capacitor having as large a capacity as possible within a limited occupation area when forming a charge storage capacitor of a semiconductor device.

〔課題を解決するための手段〕[Means for solving the problem]

上記目的は、位相シフトパターンの電子線露光時に、
帯電防止手段を具備したプロセスを使用することにより
達成される。
The above objective is for electron beam exposure of the phase shift pattern,
This is achieved by using a process with antistatic means.

帯電防止はガラス基板、位相シフト膜、電子線レジス
トのいづれかに導電性を持たせるか、あるいは、各層の
間あるいはレジスト上に導電膜を介在させることにより
達成される。すなわち、電位がアースされるような構造
にすることが必要である。また、本発明は、半導体装置
の電荷蓄積キャパシタのパターン群を形成する工程を含
む半導体装置の製造方法であって、遮光部で囲まれた光
透過領域の中に透過光の位相が該光透過部を透過した光
の位相と反転する位相シフト部が市松模様に配置され、
最外周の位相シフト部は、端部が前記遮光領域と接する
位置に形成されているホトマスクに、光を照射して、前
記遮光部と互いに位相が反転した前記位相シフト部の透
過光と該位相シフト部が形成されていない光透過領域の
透過光の干渉により、前記半導体ウエハに前記ホトマス
クの前記位相シフト部に対応する前記蓄積電荷のキャパ
シタのパターン群を露光してパターン形成することを特
徴とする半導体装置の製造方法により、達成される。
Antistatic can be achieved by imparting conductivity to any of the glass substrate, the phase shift film, and the electron beam resist, or by interposing a conductive film between each layer or on the resist. That is, it is necessary to make the structure such that the potential is grounded. The present invention also relates to a method of manufacturing a semiconductor device including a step of forming a pattern group of a charge storage capacitor of the semiconductor device, wherein the phase of the transmitted light is set in a light transmitting region surrounded by a light shielding portion. The phase shift part that inverts the phase of the light transmitted through the part is arranged in a checkered pattern,
The outermost phase shift portion irradiates light to a photomask formed at a position where an end portion is in contact with the light-shielding region, and transmits light of the phase shift portion having a phase inverted with respect to the light-shielding portion and the phase shift portion. It is characterized in that the semiconductor wafer is exposed to a pattern group of the capacitor of the stored charge corresponding to the phase shift section of the photomask to form a pattern by interference of transmitted light in a light transmission area where a shift section is not formed. This is achieved by a method of manufacturing a semiconductor device described below.

〔実施例〕〔Example〕

[参考例] 以下、本発明の一実施例を第1図により説明する。 Reference Example An embodiment of the present invention will be described below with reference to FIG.

第1図aに示すように、ガラス基板1上に通常の方法
でCrから成る遮光膜2を形成する。次に通常の方法で透
過部2−1,2−2,2−3から成る原画パターンと合わせタ
ーゲツトパターン2−4を同時に形成する。次に位相シ
フト層3を全面に被着した。
As shown in FIG. 1A, a light-shielding film 2 made of Cr is formed on a glass substrate 1 by an ordinary method. Next, the target pattern 2-4 is simultaneously formed with the original pattern composed of the transmission portions 2-1 2-2, 2-3 by a usual method. Next, the phase shift layer 3 was applied on the entire surface.

次に第1図bに示すように、全面にレジスト4を被着
し、合わせターゲツト部5のみレジスト及び位相シフト
層を除去した。しかる後、合わせターゲツトパターン2
−4のCr膜をマスクとしてガラス基板1をエツチングし
凹形状の合わせターゲツトパターン6を形成した。レジ
スト4を除去した後第1図Cに示すように、電子線レジ
スト7を全面に形成し、さらにその上にAl膜を50nmの厚
さで形成した。Al膜は帯電防止用のものであり、膜厚10
0nm以下で十分である。しかる後、所望の位置に電子線
9で位相シフトパターンを描画した。この時のパターン
位置合わせはターゲツトパターン6を用いた。ターゲツ
トパターン6は深い凹パターンであるため、ターゲツト
からの二次電子像が鮮明であり、良好な合わせ精度が得
られた。なお、Crパターンのみのターゲツトでは良好な
信号像が得られず、パターン合わせは困難であつた。
Next, as shown in FIG. 1B, a resist 4 was applied on the entire surface, and the resist and the phase shift layer were removed only from the alignment target portion 5. After a while, match target pattern 2
The glass substrate 1 was etched using the -4 Cr film as a mask to form a concave matching target pattern 6. After the resist 4 was removed, as shown in FIG. 1C, an electron beam resist 7 was formed on the entire surface, and an Al film was formed thereon with a thickness of 50 nm. The Al film is for antistatic and has a film thickness of 10
0 nm or less is sufficient. Thereafter, a phase shift pattern was drawn at a desired position with the electron beam 9. At this time, the target pattern 6 was used for pattern alignment. Since the target pattern 6 is a deep concave pattern, the secondary electron image from the target was clear and good alignment accuracy was obtained. A good signal image could not be obtained with a target consisting only of the Cr pattern, and pattern matching was difficult.

次に第1図dに示すように、アルカリ系の現像液を電
子線レジスト7の現像感度以下の濃度に調合し、この液
によりAl膜8を除去した。次に現像液濃度をレジスト現
像に好適な濃度に調合し現像を行ないレジストパターン
4′を形成した。この時、Al膜除去はレジスト現像液を
希釈して用いたため、レジストの変質等は発生せず次の
現像を良好な特性で行なうことができた。次にレジスト
パターン4′をマスクとして位相シフト層3をエツチン
グし、位相シフトパターン3′を形成した。次にレジス
トパターン4′を除去し、位相シフト型レテイクルが作
成できた。
Next, as shown in FIG. 1D, an alkali-based developer was prepared at a concentration lower than the developing sensitivity of the electron beam resist 7, and the Al film 8 was removed with this solution. Next, the concentration of the developing solution was adjusted to a concentration suitable for resist development, and development was performed to form a resist pattern 4 '. At this time, the removal of the Al film was performed by diluting the resist developing solution, so that the next development could be performed with good characteristics without deterioration of the resist. Next, the phase shift layer 3 was etched using the resist pattern 4 'as a mask to form a phase shift pattern 3'. Next, the resist pattern 4 'was removed, and a phase shift type reticle was produced.

上記実施例では位相シフト層3には塗布ケイ素化合物
を用い、膜厚tは照明光の位相反転条件1式を満足する
値とした。
In the above embodiment, a coating silicon compound was used for the phase shift layer 3, and the film thickness t was a value satisfying the phase inversion condition 1 of the illumination light.

ここでλ=365nm,n=1.47である。この時t=388nmと
なり、本実施例では390nmとした。電子線レジストはRD
−2000N(日立化成工業KK)を用い、現像液はNMD−3
(東京応化工業KK)を用いた。
Here, λ = 365 nm and n = 1.47. At this time, t = 388 nm, and in this embodiment, it is 390 nm. Electron beam resist is RD
-2000N (Hitachi Kasei Kogyo KK) using NMD-3
(Tokyo Ohka Kogyo KK) was used.

レジストをマスクとした位相シフト層3のエツチング
には弗化水素酸の希釈液を用いた。パターン2−3及び
2−1上の位相シフト層のエツチングが終ると基板ガラ
スが露光しエツチングされる心配が有るが、位相シフト
材である塗布ケイ素化合物のエツチング速度が基板ガラ
スの約10倍であつたので問題とならなかつた。材料によ
つて基板とのエツチングの選択比が小さい場合が有る。
この場合は、位相シフト層と基板の間にエツチングのス
トツプ層を介在させることが望ましい。
A dilute solution of hydrofluoric acid was used for etching the phase shift layer 3 using the resist as a mask. When the etching of the phase shift layers on the patterns 2-3 and 2-1 is finished, there is a concern that the substrate glass is exposed and etched, but the etching speed of the coated silicon compound as the phase shift material is about 10 times that of the substrate glass. It was no longer a problem. Depending on the material, the etching selectivity with the substrate may be small.
In this case, it is desirable to interpose an etching stop layer between the phase shift layer and the substrate.

本実施例で上記条件で行つたが、これに限るものでは
なく、たとえば、ガラス基板とCr膜の間あるいはCrパタ
ーン形成後全面に導電膜を形成しても同様の効果が得ら
れる。あるいは、単層の電子線レジスト7を多層レジス
トとしてその多層膜のいずれかを導電膜とすることも有
効である。また、露光波長も、365nmに限らず、他の紫
外線、エキシマレーザ光などでも有効なことは言うまで
もない。
Although the present embodiment is performed under the above conditions, the present invention is not limited to this. For example, a similar effect can be obtained by forming a conductive film between the glass substrate and the Cr film or on the entire surface after forming the Cr pattern. Alternatively, it is also effective to use the single-layer electron beam resist 7 as a multilayer resist and to use any one of the multilayer films as a conductive film. Also, the exposure wavelength is not limited to 365 nm, and it goes without saying that other ultraviolet rays, excimer laser light, and the like are also effective.

また、本実施例の変形として、位相シフト層3が遮光
膜2とガラス基板1の間に有る場合についても、ほぼ同
様の工程で位相シフト型レテイクルが作成できる。たと
えば、用いるレテイクルブランスの構造をガラス基板、
Si3N4,SiO2,Crの4層構造としたのが代表例である。こ
こでSi3N4膜は位相シフト層となるSiO2の不要部分をエ
ツチング除去する際のガラス基板のエツチングを防止す
る役目をする。SiO2は位相シフト層、Crは遮光膜であ
る。上記、構造は一例であり、これに限らず、ガラス基
板と位相シフト材料のエツチング選択比が十分大きい場
合、エツチングストツパーは不要である。さらに上記材
料もこれに限らず、本発明の目的を満足するものであれ
ば他の材料を用いても良い。
In addition, as a modification of the present embodiment, a phase shift type reticle can be created in substantially the same process even when the phase shift layer 3 is provided between the light shielding film 2 and the glass substrate 1. For example, the structure of the reticle brace used is a glass substrate,
A typical example is a four-layer structure of Si 3 N 4 , SiO 2 , and Cr. Here, the Si 3 N 4 film serves to prevent the etching of the glass substrate when the unnecessary portion of SiO 2 serving as the phase shift layer is removed by etching. SiO 2 is a phase shift layer, and Cr is a light shielding film. The above structure is an example, and the present invention is not limited to this. When the etching selectivity between the glass substrate and the phase shift material is sufficiently large, the etching stopper is unnecessary. Further, the above materials are not limited thereto, and other materials may be used as long as the objects of the present invention are satisfied.

[実施例1] 本発明の第2の実施例を以下に説明する。ここでは特
に微細スペース形成に好適な位相シフト型マスク構造を
示す。第2図に本発明のマスク構造と、このマスクで得
られる透過光の振幅およびこれに対応するウエーハ上で
の光強度を示す。第2図(a)に示すようにガラス基板
10にCrからなる遮光膜11が形成されており透過部12内
に、透明膜からなる位相シフタ13を形成した。このマス
クを透過した光の振幅分布は第2図(b)に示すよう
に、位相シフタの有る部分の位相が反転する。この光が
ウエーハ上に投影されると、第2図(c)に示すよう
に、光強度は位相の反転部で0となり、ネガレジストを
使つたパターン形成では極微細な溝が形成される。
Embodiment 1 A second embodiment of the present invention will be described below. Here, a phase shift mask structure particularly suitable for forming a fine space is shown. FIG. 2 shows the mask structure of the present invention, the amplitude of the transmitted light obtained by this mask, and the corresponding light intensity on the wafer. As shown in FIG. 2 (a), a glass substrate
A light-shielding film 11 made of Cr is formed on 10, and a phase shifter 13 made of a transparent film is formed in the transmission part 12. As shown in FIG. 2B, the amplitude distribution of the light transmitted through the mask is such that the phase of the portion having the phase shifter is inverted. When this light is projected on the wafer, the light intensity becomes 0 at the phase inversion portion as shown in FIG. 2 (c), and an extremely fine groove is formed in the pattern formation using the negative resist.

本実施例の改良例として、位相反転の境界部に遮光膜
を設けることにより、線幅制御の良好なパターン形成が
可能となる。
As an improved example of this embodiment, by providing a light-shielding film at the boundary of phase inversion, it becomes possible to form a pattern with good line width control.

[実施例2] 実施例2のマスク構造を半導体記憶素子の製造に適用
した例を示す。DRAMダイナミツク ランダム アクセス
メモリ:Dynamic Random Access Memory)の代表的な
セル構造である積層容量型セルの製造工程における蓄積
容量部のパターン形成に実施例2の位相シフト型マスク
を用いた。
Second Embodiment An example in which the mask structure of the second embodiment is applied to the manufacture of a semiconductor memory device will be described. The phase shift type mask of the second embodiment was used to form a pattern of a storage capacitor portion in a manufacturing process of a stacked capacitor type cell having a typical cell structure of a DRAM dynamic random access memory (Dynamic Random Access Memory).

第3図に従来法で得られたパターンと本発明によるパ
ターンの平面形状を示した。第3図(a)は従来法のマ
スクを用いて得られたパターン形状を示す。蓄積容量部
13の間隔14はリソグラフイの解像限界まで微細化できた
が、それ以下の寸法ではパターン間でシヨートが発生し
た。ここで用いた開口数0.42のi線(365nm)用レンズ
では解像限界は0.5μmであつた。これに対し、第3図
(b)に示すように、本発明を適用した例では蓄積容量
部13′の間隔14′のレンズの解像限界以下まで微細化で
き、0.1μmの間隔が解像できた。
FIG. 3 shows the planar shapes of the pattern obtained by the conventional method and the pattern according to the present invention. FIG. 3A shows a pattern shape obtained by using a conventional mask. Storage capacity section
Although the interval 14 of 13 could be miniaturized to the resolution limit of lithography, shorts occurred between patterns with dimensions smaller than that. The i-line (365 nm) lens having a numerical aperture of 0.42 used here had a resolution limit of 0.5 μm. On the other hand, as shown in FIG. 3 (b), in the example to which the present invention is applied, the resolution can be reduced to below the resolution limit of the lens of the interval 14 'of the storage capacitor portion 13', and the interval of 0.1 μm can be resolved. did it.

したがつて、本発明によれば、従来法の蓄積容量部の
配列ピツチ15と同一ピツチにもかかわらず、蓄積容量部
の面積を大幅に増大できる。本実施例で製造したDRAMの
蓄積容量を測定した結果、メモリ1ビツト当り本発明で
は38fFとなり、従来法の20fFに対し、約2倍の容量が得
られ、信頼性の高い素子が製造できた。別の見方をすれ
ば従来法と同じ蓄積容量面積で良い場合は間隔15をより
小さくすることが可能であり、セル面積の縮小が実現で
き、チツプサイズの縮小化が達成できる。
Therefore, according to the present invention, the area of the storage capacitor section can be greatly increased despite the same pitch as the arrangement pitch 15 of the storage capacitor section in the conventional method. As a result of measuring the storage capacity of the DRAM manufactured in this example, it was 38 fF per bit of memory in the present invention, which was about double the capacity of 20 fF of the conventional method, and a highly reliable element was manufactured. . From another viewpoint, when the same storage capacity area as that of the conventional method is sufficient, the interval 15 can be made smaller, the cell area can be reduced, and the chip size can be reduced.

〔発明の効果〕〔The invention's effect〕

以上のように本発明によれば、位相シフトパターンの
電子線露光時に基板の帯電は発生せず、良好な位相シフ
トパターンが形成できる。たとえば本実施例において
は、原画パターンと位相シフトパターンの位置ずれは0.
3μm以下であり、得られたパターンの寸法精度も±0.2
μm以下であつた。
As described above, according to the present invention, the substrate is not charged during the electron beam exposure of the phase shift pattern, and a good phase shift pattern can be formed. For example, in the present embodiment, the displacement between the original image pattern and the phase shift pattern is 0.
3μm or less, and the dimensional accuracy of the obtained pattern is ± 0.2
μm or less.

さらに位相シフトマスクの特性を十分に生かしたマス
ク構造により、超微細なパターンの形成も可能となり、
半導体記憶素子等の特性改善あるいは面積の縮小化にも
有効である。
In addition, a mask structure that makes full use of the characteristics of the phase shift mask makes it possible to form ultra-fine patterns,
It is also effective for improving characteristics or reducing the area of a semiconductor memory element or the like.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明のホトマスクの製造工程を示す断面図、
第2図は本発明のマスク構造を示す断面図、および、得
られる透過光の振幅分布及び光強度を示す図、第3図は
従来例と本発明の実施例による形成パターンの平面図で
ある。 1,10……ガラス基板、2,11……遮光膜Cr、3,13……位相
シフト層、7……電子線レジスト、8……Al、13……蓄
積容量部。
FIG. 1 is a sectional view showing a manufacturing process of a photomask of the present invention,
FIG. 2 is a cross-sectional view showing the mask structure of the present invention and a diagram showing the amplitude distribution and light intensity of the obtained transmitted light, and FIG. 3 is a plan view of a formed pattern according to the conventional example and the embodiment of the present invention. . 1,10: glass substrate, 2,11: light-shielding film Cr, 3,13: phase shift layer, 7: electron beam resist, 8: Al, 13: storage capacitor section.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 寺澤 恒男 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 木村 紳一郎 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (56)参考文献 特開 昭55−79447(JP,A) 特開 昭62−195120(JP,A) 特開 昭61−292643(JP,A) 特開 昭58−173744(JP,A) 特開 昭62−92438(JP,A) 特開 昭62−189468(JP,A) 特開 平2−34854(JP,A) (58)調査した分野(Int.Cl.6,DB名) G03F 1/00 - 1/16 H01L 21/30──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tsuneo Terasawa 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Shinichiro Kimura 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. (56) References JP-A-55-79447 (JP, A) JP-A-62-195120 (JP, A) JP-A-61-292463 (JP, A) JP-A-58-173744 (JP, A) A) JP-A-62-92438 (JP, A) JP-A-62-189468 (JP, A) JP-A-2-34854 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) ) G03F 1/00-1/16 H01L 21/30

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体装置の電荷蓄積キャパシタのパター
ン群を形成する工程を含む半導体装置の製造方法であっ
て、遮光部で囲まれた光透過領域の中に透過光の位相が
該光透過部を透過した光の位相と反転する位相シフト部
が市松模様に配置され、最外周の位相シフト部は、端部
が前記遮光領域と接する位置に形成されているホトマス
クに、光を照射して、前記遮光部と互いに位相が反転し
た前記位相シフト部の透過光と該位相シフト部が形成さ
れていない光透過領域の透過光の干渉により、前記半導
体ウエハに前記ホトマスクの前記位相シフト部に対応す
る前記蓄積電荷のキャパシタのパターン群を露光してパ
ターン形成することを特徴とする半導体装置の製造方
法。
1. A method of manufacturing a semiconductor device, comprising: forming a pattern group of a charge storage capacitor of a semiconductor device, wherein a phase of a transmitted light in a light transmitting region surrounded by a light shielding portion is set in the light transmitting portion. A phase shift portion that inverts the phase of the light transmitted therethrough is arranged in a checkered pattern, and the outermost phase shift portion irradiates light to a photomask formed at a position where an end portion is in contact with the light shielding region, The semiconductor wafer corresponds to the phase shift portion of the photomask on the semiconductor wafer due to interference between transmitted light of the phase shift portion having a phase inverted with respect to the light shielding portion and transmitted light of a light transmission region where the phase shift portion is not formed. A method of manufacturing a semiconductor device, comprising: exposing a pattern group of a capacitor of the stored charge to form a pattern.
【請求項2】前記位相シフト部と前記光透過領域の位相
反転の境界部に線幅制御のための遮光膜が設けられてい
ることを特徴とする請求項1に記載の半導体装置の製造
方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein a light-shielding film for controlling line width is provided at a boundary between the phase shift portion and the phase inversion of the light transmitting region. .
【請求項3】半導体装置の電荷蓄積キャパシタのパター
ン群を形成する工程を含む半導体装置の製造方法であっ
て、遮光部で囲まれた光透過領域の中に透過光の位相が
該光透過部を透過した光の位相と反転する位相シフト部
が二次元的に複数配置らえ、最外周の位相シフト部は、
端部が前記遮光領域と接する位置に形成されているホト
マスクに光を照射して、前記位相シフト部を透過した光
と該位相シフト部が形成されていない光透過領域を透過
した光の干渉により、前記半導体ウエハに前記蓄積電荷
キャパシタが碁盤の目状に配置されたパターンを形成す
ることを特徴とする半導体装置の製造方法。
3. A method for manufacturing a semiconductor device, comprising a step of forming a pattern group of a charge storage capacitor of a semiconductor device, wherein a phase of transmitted light is set in a light transmitting region surrounded by a light shielding portion. A plurality of two-dimensionally arranged phase shift units that invert the phase of light transmitted therethrough, and the outermost phase shift unit is
By irradiating light to a photomask formed at a position where an end portion is in contact with the light shielding region, interference between light transmitted through the phase shift portion and light transmitted through a light transmission region where the phase shift portion is not formed is caused. Forming a pattern in which the stored charge capacitors are arranged in a grid pattern on the semiconductor wafer.
【請求項4】遮光領域と、第一の光透過領域と、透過光
の位相が前記第一の光透過領域を透過した光の位相と反
転し前記第一の光透過領域と前記遮光膜を介して隣接す
る第二の光透過領域を有するマスクに光を照射して、半
導体装置の電荷蓄積キャパシタが碁盤の目状に配置され
たパターンを形成することを特徴とする半導体装置の製
造方法。
4. The light-shielding region, the first light-transmitting region, and the phase of the transmitted light is inverted from the phase of the light transmitted through the first light-transmitting region, and the first light-transmitting region and the light-shielding film are separated from each other. A method of manufacturing a semiconductor device, comprising irradiating a mask having a second light transmissive region adjacent thereto through a light to form a pattern in which charge storage capacitors of the semiconductor device are arranged in a grid pattern.
JP22866988A 1988-09-14 1988-09-14 Method for manufacturing semiconductor device Expired - Lifetime JP2810061B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22866988A JP2810061B2 (en) 1988-09-14 1988-09-14 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22866988A JP2810061B2 (en) 1988-09-14 1988-09-14 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0278216A JPH0278216A (en) 1990-03-19
JP2810061B2 true JP2810061B2 (en) 1998-10-15

Family

ID=16879957

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2810061B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5298365A (en) 1990-03-20 1994-03-29 Hitachi, Ltd. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
JPH05241321A (en) * 1992-02-28 1993-09-21 Hitachi Ltd Optical mask and method for correcting this mask
JPH05165189A (en) * 1991-12-12 1993-06-29 Hitachi Ltd Optical mask and method for correcting the mask
US5246800A (en) * 1991-09-12 1993-09-21 Etec Systems, Inc. Discrete phase shift mask writing
JP2874406B2 (en) * 1991-10-09 1999-03-24 株式会社日立製作所 Defect repair method for phase shifter mask
US5418095A (en) * 1993-01-21 1995-05-23 Sematech, Inc. Method of fabricating phase shifters with absorbing/attenuating sidewalls using an additive process
US5411824A (en) * 1993-01-21 1995-05-02 Sematech, Inc. Phase shifting mask structure with absorbing/attenuating sidewalls for improved imaging
WO1994017449A1 (en) * 1993-01-21 1994-08-04 Sematech, Inc. Phase shifting mask structure with multilayer optical coating for improved transmission

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5579447A (en) * 1978-12-09 1980-06-14 Dainippon Printing Co Ltd Photomask substrate and photomask
DE3374452D1 (en) * 1982-04-05 1987-12-17 Ibm Method of increasing the image resolution of a transmitting mask and improved masks for performing the method
JPH0690504B2 (en) * 1985-06-21 1994-11-14 株式会社日立製作所 Photomask manufacturing method
JPH0738372B2 (en) * 1985-10-18 1995-04-26 工業技術院長 Pattern formation method
JPH0690507B2 (en) * 1986-02-17 1994-11-14 株式会社日立製作所 Photomask, projection exposure method using the same, and method of manufacturing photomask
JPS62195120A (en) * 1986-02-21 1987-08-27 Sumitomo Electric Ind Ltd Alignment mark processing of semiconductor integrated circuit
JP2865685B2 (en) * 1988-03-16 1999-03-08 株式会社日立製作所 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH0278216A (en) 1990-03-19

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