JPH03222409A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03222409A JPH03222409A JP1840490A JP1840490A JPH03222409A JP H03222409 A JPH03222409 A JP H03222409A JP 1840490 A JP1840490 A JP 1840490A JP 1840490 A JP1840490 A JP 1840490A JP H03222409 A JPH03222409 A JP H03222409A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist film
- photoresist film
- resin film
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 68
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000011347 resin Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 19
- 238000011161 development Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 21
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 238000000926 separation method Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000012546 transfer Methods 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000004372 Polyvinyl alcohol Substances 0.000 description 9
- 229920002451 polyvinyl alcohol Polymers 0.000 description 9
- 238000002955 isolation Methods 0.000 description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920003986 novolac Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- QTWJRLJHJPIABL-UHFFFAOYSA-N 2-methylphenol;3-methylphenol;4-methylphenol Chemical compound CC1=CC=C(O)C=C1.CC1=CC=CC(O)=C1.CC1=CC=CC=C1O QTWJRLJHJPIABL-UHFFFAOYSA-N 0.000 description 1
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229930003836 cresol Natural products 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- -1 naphthoquinonediazide sulfonic acid ester Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野コ
本発明はフォトレジスト膜を使用して被加工膜を所望の
パターンに成形する半導体装置の製造方法に関し、特に
MO8型集積回路等のように半導体基板表面に段差を有
する半導体装置にゲート電極を形成する場合に好適の半
導体装置の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device in which a photoresist film is used to form a film to be processed into a desired pattern, and particularly to a method for manufacturing a semiconductor device such as an MO8 type integrated circuit. The present invention relates to a method of manufacturing a semiconductor device suitable for forming a gate electrode on a semiconductor device having a step on the surface of a semiconductor substrate.
[従来の技術]
MO8型集積回路においては、ゲート電極の寸法が集積
回路装置の特性及び製造歩留りに大きな影響を与える。[Prior Art] In MO8 type integrated circuits, the dimensions of the gate electrode have a great influence on the characteristics and manufacturing yield of the integrated circuit device.
このため、ゲート電極形成工程においては、寸法精度を
厳しく管理する必要がある。Therefore, in the gate electrode forming process, it is necessary to strictly control dimensional accuracy.
第3図は従来の半導体装置の製造方法の1例を示す断面
図である。FIG. 3 is a cross-sectional view showing an example of a conventional method for manufacturing a semiconductor device.
先ず、半導体基板21の素子分離領域に絶縁分離層22
を選択的に形成する。そして、基板21の全面にゲート
電極となるシリコン多結晶層23を被覆形成する。この
場合に、絶縁分離層22が形成されている素子分離領域
と絶縁分離層22が形成されていない活性領域との境界
部において、シリコン多結晶層23に段差が形成される
。First, an insulating isolation layer 22 is formed in an element isolation region of a semiconductor substrate 21.
selectively formed. Then, the entire surface of the substrate 21 is coated with a silicon polycrystalline layer 23 that will become a gate electrode. In this case, a step is formed in the silicon polycrystalline layer 23 at the boundary between the element isolation region where the insulation isolation layer 22 is formed and the active region where the insulation isolation layer 22 is not formed.
次に、このシリコン多結晶層23上に約1.2μmの厚
さでポジティブ型フォトレジスト膜24を形成する。そ
して、波長が43Gnmのg線を使用する縮小投影露光
装置により、フォトレジスト膜24に所定のマスクパタ
ーンを転写する。Next, a positive photoresist film 24 is formed on this silicon polycrystalline layer 23 to a thickness of about 1.2 μm. Then, a predetermined mask pattern is transferred onto the photoresist film 24 using a reduction projection exposure apparatus that uses G-line having a wavelength of 43 Gnm.
次に、テトラメチルアンモニウムハイドロオキサイド(
TMAH)を主成分とする有機アルカリ現像液を使用し
て、フォトレジスト膜24に現像処理を施す。これによ
り、所定のパターンのレジスト膜を得る。その後、ポス
トベーク処理を施した後、このレジスト膜をマスクとし
、平行平板型リアクティブイオンエツチング装置を使用
して、シリコン多結晶層23にドライエツチングを施す
。Next, tetramethylammonium hydroxide (
The photoresist film 24 is developed using an organic alkaline developer containing TMAH as a main component. In this way, a resist film with a predetermined pattern is obtained. Thereafter, after a post-baking process is performed, the polycrystalline silicon layer 23 is dry etched using a parallel plate type reactive ion etching apparatus using this resist film as a mask.
これにより、シリコン多結晶層23は所定のゲート電極
パターンに成形される。Thereby, the silicon polycrystalline layer 23 is formed into a predetermined gate electrode pattern.
次いで、レジスト膜をプラズマ又は酸により剥離する。Next, the resist film is removed using plasma or acid.
このようにして、所定のゲート電極を有する半導体装置
を製造することができる。In this way, a semiconductor device having a predetermined gate electrode can be manufactured.
[発明が解決しようとする課題]
しかしながら、上述した従来の半導体装置の製造方法に
は、面積が異なる複数の活性領域に所定の幅でゲート電
極等を形成しようとすると、寸法精度を高精度で制御す
ることができなくなるという欠点がある。以下に、その
理由について説明する。[Problems to be Solved by the Invention] However, in the conventional semiconductor device manufacturing method described above, when trying to form gate electrodes and the like with a predetermined width in multiple active regions having different areas, it is difficult to maintain dimensional accuracy with high precision. The disadvantage is that it cannot be controlled. The reason for this will be explained below.
第4図は、半導体基板上に塗布されたフォトレジスト膜
に幅が1μmの線を1μmの間隔で配列したパターンを
g線縮小投影露光装置を使用して転写したときのフォト
レジスト膜の膜厚とレジストパターンの線幅との関係を
示すグラフ図である。Figure 4 shows the film thickness of a photoresist film when a pattern in which lines with a width of 1 μm are arranged at 1 μm intervals is transferred onto a photoresist film coated on a semiconductor substrate using a G-line reduction projection exposure device. FIG. 4 is a graph diagram showing the relationship between the line width of the resist pattern and the line width of the resist pattern.
第4図は横軸にフォトレジスト膜の膜厚をとり、縦軸に
フォトレジスト膜と基板との界面におけるレジストパタ
ーンの線幅をとっである。In FIG. 4, the horizontal axis represents the thickness of the photoresist film, and the vertical axis represents the line width of the resist pattern at the interface between the photoresist film and the substrate.
この第4図から明らかなように、フォトレジスト膜の膜
厚に対して、転写したパターンの線幅が正弦波状に変化
する。この現象は干渉効果として知られている。この干
渉効果は、基板上に塗布されたフォトレジスト膜に入射
した単波長の露光光が基板から反射してきた反射光と干
渉し、このためフォトレジスト膜の厚さ方向で吸収され
る光エネルギー量が異なってしまうことに起因して発生
する。この干渉効果のために、フォトレジスト膜の膜厚
のバラツキが現像処理後のレジスト膜のパターン幅のバ
ラツキに影響を与える。従って、フォトレジスト膜の膜
厚は可及的に均一であることが好ましい。As is clear from FIG. 4, the line width of the transferred pattern changes sinusoidally with respect to the film thickness of the photoresist film. This phenomenon is known as the interference effect. This interference effect occurs when the single-wavelength exposure light incident on the photoresist film coated on the substrate interferes with the reflected light reflected from the substrate, resulting in the amount of light energy absorbed in the thickness direction of the photoresist film. This occurs due to differences in the numbers. Due to this interference effect, variations in the thickness of the photoresist film affect variations in the pattern width of the resist film after development. Therefore, it is preferable that the thickness of the photoresist film is as uniform as possible.
ところで、絶縁分離層により素子分離され、面積が相互
に異なる種々の活性領域を有する半導体基板上にフォト
レジスト膜をスピンフートにより形成すると、第3図に
示すように、活性領域が狭い部位のフォトレジスト膜の
膜厚d1と広い部位のフォトレジスト膜の膜厚d2とは
一異なり、活性領域の面積に応じてフォトレジスト膜の
膜厚が変化してしまう。By the way, when a photoresist film is formed by spin footing on a semiconductor substrate which is separated by an insulating separation layer and has various active regions with different areas, as shown in FIG. The thickness d1 of the film is completely different from the thickness d2 of the photoresist film in a wide area, and the thickness of the photoresist film changes depending on the area of the active region.
第5図は横軸に活性領域の面積S(μm2)の対数をと
り、縦軸にフォトレジスト膜の膜厚をとって、両者の関
係を示したグラフ図である。この第5図から明らかなよ
うに、活性領域の面積が大きくなると、フォトレジスト
膜の膜厚は薄くなってしまう。FIG. 5 is a graph showing the relationship between the logarithm of the area S (μm2) of the active region on the horizontal axis and the thickness of the photoresist film on the vertical axis. As is clear from FIG. 5, as the area of the active region increases, the thickness of the photoresist film becomes thinner.
第8図は、面積Sが相互に異なる3種類の活性領域をス
ピンコードにより形成したフォトレジスト膜で被覆し、
各活性領域のフォトレジスト膜に同一の幅のゲート電極
パターンを転写した後、レジスト膜のパターン幅を調べ
た結果を示すグラフ図である。この第6図から明らかな
ように、活性領域の面積が異なることにより、0.17
μm程度のパターン寸法偏差が発生する。従って、従来
の方法においては、ゲート電極等の寸法を高精度で制御
することが困難である。FIG. 8 shows that three types of active regions with different areas S are covered with a photoresist film formed by a spin code.
FIG. 7 is a graph showing the results of examining the pattern width of the resist film after transferring a gate electrode pattern of the same width to the photoresist film of each active region. As is clear from FIG. 6, due to the difference in the area of the active region, 0.17
Pattern dimensional deviation on the order of μm occurs. Therefore, in the conventional method, it is difficult to control the dimensions of the gate electrode and the like with high precision.
なお、干渉効果の外にフォトレジスト膜の膜厚がレジス
トパターン幅に影響を与えるものとして、バルク効果が
ある。即ち、露光後のフォトレジスト膜を現像して得た
レジスト膜のパターンは、その上部の幅よりも底部の幅
の方が若干広くなる。In addition to the interference effect, the thickness of the photoresist film influences the width of the resist pattern due to the bulk effect. That is, the pattern of the resist film obtained by developing the photoresist film after exposure is slightly wider at the bottom than at the top.
このため、フォトレジスト膜の膜厚が異なると、現像処
理後のレジスト膜のパターン幅にバラツキが発生する。For this reason, if the film thickness of the photoresist film differs, variations will occur in the pattern width of the resist film after development processing.
しかしながら、通常のゲート電極パターンの場合、この
バルク効果によりレジスト膜のパターン幅が変化する割
合は、干渉効果に比して極めて小さい。However, in the case of a normal gate electrode pattern, the rate at which the pattern width of the resist film changes due to this bulk effect is extremely small compared to the interference effect.
本発明はかかる問題点に鑑みてなされたものであって、
干渉効果によるパターン寸法偏差が抑制され、転写パタ
ーンの寸法を高精度で制御することができる半導体装置
の製造方法を提供することを目的とする。The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which pattern dimension deviation due to interference effects is suppressed and the dimensions of a transferred pattern can be controlled with high precision.
[課題を解決するための手段]
本発明に係る半導体装置の製造方法は、半導体基板上に
被加工膜を形成する工程と、この被加工膜上にフォトレ
ジスト膜を形成する工程と、このフォトレジスト膜上に
露光光に対して透光性を有する樹脂膜を形成する工程と
、この樹脂膜を介して露光することにより前記フォトレ
ジスト膜に所定のパターンを転写する工程と、前記透光
性樹脂膜を除去する工程と、前記フォトレジスト膜に現
像処理を施して前記所定のパターンのレジスト膜を形成
する工程と、このレジスト膜をマスクとして前記被加工
膜を前記所定のパターンに成形する工程とを有すること
を特徴とする。[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a step of forming a film to be processed on a semiconductor substrate, a step of forming a photoresist film on the film to be processed, and a step of forming a photoresist film on the film to be processed. a step of forming a resin film that is transparent to exposure light on the resist film; a step of transferring a predetermined pattern to the photoresist film by exposing through the resin film; a step of removing the resin film; a step of developing the photoresist film to form a resist film with the predetermined pattern; and a step of forming the processed film into the predetermined pattern using the resist film as a mask. It is characterized by having the following.
[作用]
本発明においては、フォトレジスト膜上に所定の露光光
に対して透光性を有する樹脂膜を形成する。この場合に
、フォトレジスト膜の膜厚が不均一であっても、例えば
屈折率がフォトレジスト膜と略々同一である透光性樹脂
膜を、フォトレジスト膜の膜厚と透光性樹脂膜の膜厚と
の和が全ての活性領域で同一になるようにフォトレジス
ト膜上に形成する。そうすると、所定のパターンで露光
した場合に、干渉効果によるレジスト膜のパターン幅の
寸法偏差が抑制される。これにより、所定の幅で高精度
でレジスト膜パターンを形成することができる。[Function] In the present invention, a resin film that is transparent to predetermined exposure light is formed on a photoresist film. In this case, even if the thickness of the photoresist film is uneven, for example, a light-transmitting resin film whose refractive index is approximately the same as that of the photoresist film may be compared to the thickness of the photoresist film. is formed on the photoresist film so that the sum of the film thicknesses is the same in all active regions. Then, when exposed in a predetermined pattern, dimensional deviations in the pattern width of the resist film due to interference effects are suppressed. Thereby, a resist film pattern can be formed with a predetermined width and high precision.
また、透光性樹脂膜の屈折率及び膜厚等を適正に選択す
ることにより、フォトレジスト膜及び透光性樹脂膜の膜
厚の和が各活性領域で異なっていても、全ての活性領域
において干渉効果による影響を同一にすることができる
。これにより、現像後のレジスト膜のパターン寸法偏差
が抑制されるため、被加工膜を所望の幅に高精度で成形
することができる。In addition, by appropriately selecting the refractive index and film thickness of the light-transmitting resin film, even if the sum of the film thicknesses of the photoresist film and the light-transmitting resin film is different for each active region, all active regions can be The influence of interference effects can be made the same in both cases. This suppresses pattern dimensional deviation of the resist film after development, so that the film to be processed can be formed to a desired width with high precision.
[実施例コ
次に、本発明の実施例について添付の図面を参照して説
明する。[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.
第1図(a)乃至(d)は本発明の第1の実施例方法を
工程順に示す断面図である。FIGS. 1(a) to 1(d) are cross-sectional views showing the method of the first embodiment of the present invention in the order of steps.
先ず、第1図(a)に示すように、半導体基板1の表面
に絶縁分離層2を選択的に形成する。そして、所定のゲ
ート電極パターンに成形すべきシリコン多結晶層3を気
相成長法により基板1の全面に形成する。その後、この
シリコン多結晶層3上にノボラック樹脂とナフトキノン
ジアジドスルホン酸エステルからなる通常のポジティブ
型フォトレジスト膜4を形成する。この場合に、面積が
大きい活性領域においては、面積が小さい活性領域に比
してフォトレジスト膜4の膜厚が薄くなる。First, as shown in FIG. 1(a), an insulating separation layer 2 is selectively formed on the surface of a semiconductor substrate 1. Then, a polycrystalline silicon layer 3 to be formed into a predetermined gate electrode pattern is formed over the entire surface of the substrate 1 by vapor phase growth. Thereafter, a normal positive type photoresist film 4 made of novolac resin and naphthoquinonediazide sulfonic acid ester is formed on this silicon polycrystalline layer 3. In this case, the thickness of the photoresist film 4 is thinner in the active region with a larger area than in the active region with a smaller area.
次に、第1図(b)に示すように、フォトレジスト膜4
上にPVA (ポリビニルアルコール)膜5を例えば5
00人の厚さで形成する。そして、例えばmt pクレ
ゾールをモノマーとするノボラック樹脂のように、g線
の透過率が高く且つ屈折率がフォトレジストに近い樹脂
を溶剤に溶解して極めて低粘度の溶液にし、スピンコー
ドによりこの溶液をPVA膜5上に塗布して透光性樹脂
膜6を形成する。この場合に、樹脂膜8の膜厚を約1.
0μmと比較的厚くして、その上面が平坦になるように
する。なお、PvA膜5の材料であるポリビニルアルコ
ールは水溶性の樹脂である。また、このPVA膜5はフ
ォトレジスト膜4と樹脂膜8とが接触して両者が混合す
ることを防止するために形成するものである。Next, as shown in FIG. 1(b), the photoresist film 4
For example, a PVA (polyvinyl alcohol) film 5 is placed on top.
Formed with a thickness of 0.00 people. Then, a resin with high G-line transmittance and a refractive index close to that of photoresist, such as a novolac resin whose monomer is mt p cresol, is dissolved in a solvent to make an extremely low viscosity solution, and this solution is processed using a spin code. is applied onto the PVA film 5 to form a transparent resin film 6. In this case, the thickness of the resin film 8 is set to about 1.
It is made relatively thick to 0 μm so that its upper surface is flat. Note that polyvinyl alcohol, which is the material of the PvA film 5, is a water-soluble resin. Further, this PVA film 5 is formed to prevent the photoresist film 4 and the resin film 8 from coming into contact with each other and mixing them.
次に、g線を露光光とする115縮小投影露光装置を使
用して、活性領域のフォトレジスト膜4に、例えば幅が
1.0μmの所定のゲート電極パターンを転写する。こ
のとき、各活性領域におけるフォトレジスト膜4及び樹
脂膜6の膜厚の和は同一であるので、干渉効果に起因す
る各活性領域の転写パターンの寸法のバラツキが抑制さ
れる。Next, a predetermined gate electrode pattern having a width of, for example, 1.0 μm is transferred onto the photoresist film 4 in the active region using a 115 reduction projection exposure apparatus that uses G-line as exposure light. At this time, since the sum of the film thicknesses of the photoresist film 4 and the resin film 6 in each active region is the same, variations in the dimensions of the transferred pattern in each active region due to interference effects are suppressed.
次に、第1図(C)に示すように、樹脂膜6を除去する
。樹脂膜θの除去は、スピンナーのスピンチャック上に
固定した半導体基板1に、例えばエチルセルソルブアセ
テ−) (ECA)をノズルから数回供給して樹脂膜6
を溶解した後、高速で基板1を回転させることにより行
なうことが好ましい。Next, as shown in FIG. 1(C), the resin film 6 is removed. The resin film θ is removed by supplying, for example, ethyl cell solve acetate (ECA) several times from a nozzle to the semiconductor substrate 1 fixed on the spin chuck of a spinner.
It is preferable to perform this by rotating the substrate 1 at high speed after dissolving the .
次に、第1図(d)に示すように、例えば濃度が2.3
8重量%のテトラメチルアンモニウムハイドロオキサイ
ド水溶液等のを機アルカリ現像液によりフォトレジスト
膜4に現像処理を施す。これにより、不要部分のフォト
レジスト膜4が除去されて所定のパターンのレジスト膜
4aが得られる。Next, as shown in FIG. 1(d), for example, the concentration is 2.3.
The photoresist film 4 is developed using an alkaline developer such as an 8% by weight aqueous solution of tetramethylammonium hydroxide. As a result, unnecessary portions of the photoresist film 4 are removed, and a resist film 4a having a predetermined pattern is obtained.
なお、PVA膜5は水溶性であるため、現像処理前のプ
リウェット処理により完全に除去する。また、プリウェ
ット処理を行なわない場合でも、現像液が基板1上に供
給されると、PVA膜5は現像液に数秒で完全に溶解し
て除去される。Note that since the PVA film 5 is water-soluble, it is completely removed by a pre-wet process before the development process. Further, even when the pre-wet process is not performed, when the developer is supplied onto the substrate 1, the PVA film 5 is completely dissolved in the developer and removed in a few seconds.
次いで、従来と同様に、レジスト膜4aをマスクとして
、シリコン多結晶層3をエツチングする。Next, as in the prior art, the silicon polycrystalline layer 3 is etched using the resist film 4a as a mask.
その後、レジスト膜4aを除去する。これにより、所定
のパターンでゲート電極を形成することができる。After that, the resist film 4a is removed. Thereby, the gate electrode can be formed in a predetermined pattern.
本実施例においては、上述の如く、屈折率がフォトレジ
スト膜4のそれと略々同一の樹脂膜6をフォトレジスト
膜4上に各活性領域におけるレジスト膜4及び樹脂膜6
の膜厚の和か略々同一になるように形成した後、フォト
レジスト膜4の露光を行なうので、干渉効果に起因する
パターン幅のバラツキが回避され、各活性領域における
ゲート電極の幅を高精度で所定値に制御することができ
る。In this embodiment, as described above, a resin film 6 having a refractive index substantially the same as that of the photoresist film 4 is coated on the photoresist film 4 in each active region.
Since the photoresist film 4 is exposed after being formed so that the sum of the film thicknesses is approximately the same, variations in pattern width due to interference effects are avoided, and the width of the gate electrode in each active region can be increased. It can be controlled to a predetermined value with precision.
第2図(a)乃至(C)は本発明の第2の実施例方法を
工程順に示す断面図である。FIGS. 2(a) to 2(C) are cross-sectional views showing the second embodiment of the method of the present invention in order of steps.
先ず、第2図(a)に示すように、第1の実施例と同様
にして、半導体基板11上に絶縁分離層12を選択的に
形成する。その後、基板11の全面にシリコン多結晶層
13及びフォトレジスト膜14を形成する。First, as shown in FIG. 2(a), an insulating isolation layer 12 is selectively formed on a semiconductor substrate 11 in the same manner as in the first embodiment. Thereafter, a silicon polycrystalline layer 13 and a photoresist film 14 are formed on the entire surface of the substrate 11.
次に、第2図(b)に示すように、フォトレジスト膜1
4上にPVA等の水溶性樹脂膜15を塗布する。その後
、露光装置により所定のパターンをフォトレジスト膜1
4に転写する。Next, as shown in FIG. 2(b), the photoresist film 1
4, a water-soluble resin film 15 such as PVA is applied. After that, a predetermined pattern is formed on the photoresist film 1 using an exposure device.
Transfer to 4.
このとき、面積が小さい活性領域のフォトレジスト膜1
4及び水溶性樹脂膜工5の膜厚を夫々d1及びt□とし
、面積が大きい活性領域のフォトレジスト膜14及び水
溶性樹脂膜15の膜厚を夫々d2及びt2とし、フォト
レジスト膜14の屈折率をnR1水溶性樹脂膜15の屈
折率をnpとすると、下記(1)式が成立すれば干渉効
果による寸法偏差を回避することができる。At this time, the photoresist film 1 in the active region, which has a small area,
The film thicknesses of the photoresist film 14 and the water-soluble resin film 15 in the large active area are d2 and t2, respectively. If the refractive index is nR1 and the refractive index of the water-soluble resin film 15 is np, then if the following formula (1) holds true, dimensional deviation due to interference effects can be avoided.
dxnR+t+np
=(LnI?+t2np ・(1)
従って、この(1)式を満足させるようにフォトレジス
ト膜14及び樹脂膜15を形成する。この場合に、フォ
トレジスト膜14の厚さdt+d2及び屈折率nRを所
望の値に設定することは、プロセスの制約上困難な場合
がある。しかし、水溶性樹脂膜15の材質及び塗布方法
等を選択することにより、樹脂膜15の厚さt8.t2
及び屈折率nPを調整して、前記(1)式を満足させる
ことができる。これにより、干渉効果に起因する転写パ
ターンの寸法のバラツキが抑制される。dxnR+t+np = (LnI?+t2np ・(1) Therefore, the photoresist film 14 and the resin film 15 are formed so as to satisfy this formula (1). In this case, the thickness dt+d2 and the refractive index nR of the photoresist film 14 are It may be difficult to set t8 to a desired value due to process constraints. However, by selecting the material and coating method of the water-soluble resin film 15, the thickness t8.t2 of the resin film 15 can be set to a desired value.
and the refractive index nP can be adjusted to satisfy the above formula (1). This suppresses variations in the dimensions of the transferred pattern due to interference effects.
次に、第2図(C)に示すように、第1の実施例と同様
にしてフォトレジスト膜14に現像処理を施す。この場
合に、水溶性樹脂膜15はプリウェット処理において除
去され、所定のパターンのレジスト膜14aを得ること
ができる。Next, as shown in FIG. 2(C), the photoresist film 14 is developed in the same manner as in the first embodiment. In this case, the water-soluble resin film 15 is removed in the pre-wet process, and a resist film 14a having a predetermined pattern can be obtained.
次いで、従来と同様に、このレジスト膜14aをマスク
として、シリコン多結晶層13をエツチングする。その
後、レジスト膜14aを除去することにより、所定のパ
ターンのゲート電極を得ることができる。Next, as in the conventional method, the silicon polycrystalline layer 13 is etched using the resist film 14a as a mask. Thereafter, by removing the resist film 14a, a gate electrode with a predetermined pattern can be obtained.
本実施例においては、上述の如く、水溶性樹脂膜15の
膜厚及び屈折率を適正に選択することにより、第1の実
施例と同様の効果を得ることができる。また、本実施例
においては、フォトレジスト膜14上に形成する樹脂膜
15が水溶性であるため、第1の実施例に比して工程数
を減少することができるという効果もある。In this embodiment, as described above, by appropriately selecting the thickness and refractive index of the water-soluble resin film 15, the same effects as in the first embodiment can be obtained. Furthermore, in this embodiment, since the resin film 15 formed on the photoresist film 14 is water-soluble, there is also the effect that the number of steps can be reduced compared to the first embodiment.
[発明の効果コ
以上説明したように本発明によれば、フォトレジスト膜
上に透光性樹脂膜を形成した後、この樹脂膜を介してフ
ォトレジスト膜に露光を行なうから、干渉効果による転
写パターンの寸法偏差を抑制することができる。このた
め、例えばMO8型集積回路において、相互に面積が異
なる複数の活性領域に、夫々所定の幅でゲート電極を形
成することができるため、集積回路装置の特性及び製造
歩留りが向上するという効果を奏する。[Effects of the Invention] As explained above, according to the present invention, after a transparent resin film is formed on a photoresist film, the photoresist film is exposed to light through this resin film, so that transfer due to interference effects is prevented. Dimensional deviation of the pattern can be suppressed. Therefore, in an MO8 type integrated circuit, for example, gate electrodes can be formed with a predetermined width in each of a plurality of active regions having different areas, which has the effect of improving the characteristics and manufacturing yield of the integrated circuit device. play.
第1図(a)乃至(d)は本発明の第1の実施例方法を
工程順に示す断面図、第2図(a)乃至(c)は本発明
の第2の実施例方法を工程順に示す断面図、第3図は従
来の半導体装置の製造方法の1例を示す断面図、第4図
は線幅及び間隔が1μmのパターンを転写したときのフ
ォトレジスト膜の膜厚と転写パターンの線幅の関係を示
すグラフ図、第5図は活性領域の面積とフォトレジスト
膜の膜厚との関係を示すグラフ図、第6図は活性領域の
面積とフォトレジスト膜に転写したパターン寸法との関
係を示すグラフ図である。
1.11,21;半導体基板、2,12,22;絶縁分
離層、3.13,23;シリコン多結晶層、4.14.
24;フォトレジスト膜、5;PVA膜、6.透光性樹
脂膜、FIGS. 1(a) to (d) are cross-sectional views showing a method according to the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to (c) are sectional views showing the method according to the second embodiment of the present invention in order of steps. 3 is a sectional view showing an example of a conventional semiconductor device manufacturing method, and FIG. 4 shows the film thickness of the photoresist film and the transferred pattern when a pattern with a line width and interval of 1 μm is transferred. A graph showing the relationship between line width, Figure 5 is a graph showing the relationship between the area of the active region and the thickness of the photoresist film, and Figure 6 is a graph showing the relationship between the area of the active region and the pattern dimensions transferred to the photoresist film. It is a graph diagram showing the relationship. 1.11, 21; semiconductor substrate, 2, 12, 22; insulating separation layer, 3.13, 23; silicon polycrystalline layer, 4.14.
24; Photoresist film, 5; PVA film, 6. Translucent resin film,
Claims (1)
被加工膜上にフォトレジスト膜を形成する工程と、この
フォトレジスト膜上に露光光に対して透光性を有する樹
脂膜を形成する工程と、この樹脂膜を介して露光するこ
とにより前記フォトレジスト膜に所定のパターンを転写
する工程と、前記透光性樹脂膜を除去する工程と、前記
フォトレジスト膜に現像処理を施して前記所定のパター
ンのレジスト膜を形成する工程と、このレジスト膜をマ
スクとして前記被加工膜を前記所定のパターンに成形す
る工程とを有することを特徴とする半導体装置の製造方
法。(1) A process of forming a film to be processed on a semiconductor substrate, a process of forming a photoresist film on the film to be processed, and a process of forming a resin film that is transparent to exposure light on the photoresist film. a step of transferring a predetermined pattern onto the photoresist film by exposing it to light through this resin film; a step of removing the light-transmitting resin film; and a development process on the photoresist film. 1. A method of manufacturing a semiconductor device, comprising: forming a resist film having the predetermined pattern using the resist film; and using the resist film as a mask, forming the film to be processed into the predetermined pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018404A JP2616091B2 (en) | 1990-01-29 | 1990-01-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018404A JP2616091B2 (en) | 1990-01-29 | 1990-01-29 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03222409A true JPH03222409A (en) | 1991-10-01 |
JP2616091B2 JP2616091B2 (en) | 1997-06-04 |
Family
ID=11970734
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Application Number | Title | Priority Date | Filing Date |
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JP2018404A Expired - Lifetime JP2616091B2 (en) | 1990-01-29 | 1990-01-29 | Method for manufacturing semiconductor device |
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JP (1) | JP2616091B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5514526A (en) * | 1992-06-02 | 1996-05-07 | Mitsubishi Chemical Corporation | Fluorine-containing composition for forming anti-reflection film on resist surface and pattern formation method |
US5631314A (en) * | 1994-04-27 | 1997-05-20 | Tokyo Ohka Kogyo Co., Ltd. | Liquid coating composition for use in forming photoresist coating films and photoresist material using said composition |
US6136505A (en) * | 1998-06-12 | 2000-10-24 | Tokyo Ohka Kogyo Co., Ltd. | Liquid coating composition for use in forming antireflective film and photoresist material using said antireflective film |
US8097397B2 (en) | 2006-09-20 | 2012-01-17 | Tokyo Ohka Kogyo Co., Ltd. | Material for formation of protective film, method for formation of photoresist pattern, and solution for washing/removal of protective film |
US8158328B2 (en) | 2007-02-15 | 2012-04-17 | Tokyo Ohka Kogyo Co., Ltd. | Composition for formation of anti-reflection film, and method for formation of resist pattern using the same |
US8216775B2 (en) | 2008-04-03 | 2012-07-10 | Tokyo Ohka Kogyo Co., Ltd. | Anti-reflection film forming material, and method for forming resist pattern using the same |
US8455182B2 (en) | 2007-06-01 | 2013-06-04 | Tokyo Ohka Kogyo Co., Ltd. | Composition for antireflection film formation and method for resist pattern formation using the composition |
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JPS4841941A (en) * | 1971-10-04 | 1973-06-19 | ||
JPS5368172A (en) * | 1976-11-30 | 1978-06-17 | Fujitsu Ltd | Production of semiconductor device |
JPH01243044A (en) * | 1988-03-25 | 1989-09-27 | Oki Electric Ind Co Ltd | Formation of resist pattern |
JPH01243053A (en) * | 1988-03-25 | 1989-09-27 | Oki Electric Ind Co Ltd | Resist pattern forming method |
-
1990
- 1990-01-29 JP JP2018404A patent/JP2616091B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS4841941A (en) * | 1971-10-04 | 1973-06-19 | ||
JPS5368172A (en) * | 1976-11-30 | 1978-06-17 | Fujitsu Ltd | Production of semiconductor device |
JPH01243044A (en) * | 1988-03-25 | 1989-09-27 | Oki Electric Ind Co Ltd | Formation of resist pattern |
JPH01243053A (en) * | 1988-03-25 | 1989-09-27 | Oki Electric Ind Co Ltd | Resist pattern forming method |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5514526A (en) * | 1992-06-02 | 1996-05-07 | Mitsubishi Chemical Corporation | Fluorine-containing composition for forming anti-reflection film on resist surface and pattern formation method |
US5631314A (en) * | 1994-04-27 | 1997-05-20 | Tokyo Ohka Kogyo Co., Ltd. | Liquid coating composition for use in forming photoresist coating films and photoresist material using said composition |
US5783362A (en) * | 1994-04-27 | 1998-07-21 | Tokyo Ohka Kogyo Co., Ltd. | Liquid coating composition for use in forming photoresist coating films and a photoresist material using said composition |
US6136505A (en) * | 1998-06-12 | 2000-10-24 | Tokyo Ohka Kogyo Co., Ltd. | Liquid coating composition for use in forming antireflective film and photoresist material using said antireflective film |
US8097397B2 (en) | 2006-09-20 | 2012-01-17 | Tokyo Ohka Kogyo Co., Ltd. | Material for formation of protective film, method for formation of photoresist pattern, and solution for washing/removal of protective film |
US8158328B2 (en) | 2007-02-15 | 2012-04-17 | Tokyo Ohka Kogyo Co., Ltd. | Composition for formation of anti-reflection film, and method for formation of resist pattern using the same |
US8455182B2 (en) | 2007-06-01 | 2013-06-04 | Tokyo Ohka Kogyo Co., Ltd. | Composition for antireflection film formation and method for resist pattern formation using the composition |
US8216775B2 (en) | 2008-04-03 | 2012-07-10 | Tokyo Ohka Kogyo Co., Ltd. | Anti-reflection film forming material, and method for forming resist pattern using the same |
Also Published As
Publication number | Publication date |
---|---|
JP2616091B2 (en) | 1997-06-04 |
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