KR970052821A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

Info

Publication number
KR970052821A
KR970052821A KR1019950052217A KR19950052217A KR970052821A KR 970052821 A KR970052821 A KR 970052821A KR 1019950052217 A KR1019950052217 A KR 1019950052217A KR 19950052217 A KR19950052217 A KR 19950052217A KR 970052821 A KR970052821 A KR 970052821A
Authority
KR
South Korea
Prior art keywords
layer
insulating
temporary
forming
insulating layer
Prior art date
Application number
KR1019950052217A
Other languages
Korean (ko)
Other versions
KR100348297B1 (en
Inventor
박승현
고상기
심필보
권우현
Original Assignee
문정환
Lg 반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019950052217A priority Critical patent/KR100348297B1/en
Publication of KR970052821A publication Critical patent/KR970052821A/en
Application granted granted Critical
Publication of KR100348297B1 publication Critical patent/KR100348297B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체소자의 커패시터 제조방법에 관한 것으로, 특히 셀부와 주변부의 단차를 낮추므로써 상호연결(interconnection)공정이 용이하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and in particular, to facilitate the interconnection process by lowering the step difference between the cell portion and the peripheral portion.

본 발명에 따른 반도체소자의 커패시터 제조방법은 반도체기판을 준비하는 단계; 상기 반도체기판상에 제1절연막과, 상기 제1절연막에 제2절연막 그리고 상기 제2절연막위에 제3절연막을 각각 형성하는 단계; 상기 제3절연막과 제2절연막 및 제1절연막을 선택적으로 제거하여 노드콘택홀을 형성하는 단계; 상기 콘택홀을 포함한 상기 제3절연막위에 제4절연막을 형성하는 단계; 상기 제4절연막을 상기 노드콘택홀 측면에만 남도록 선택적으로 제거하여 측벽을 형성하는 단계; 상기 측벽을 포함한 콘택홀 및 제3절연막의 노출된 표면위에 제1도전층을 형성하는 단계; 상기 제1도전층위에 제5절연막을 형성하는 단계; 상기 노드콘택홀을 제외한 부분의 상기 제5절연막과 제1도전층 및 제3절연막을 선택적으로 제거하여 제2임시막과 스토리지노드 및 제1임시막을 각각 형성하는 단계; 상기 제2임시막과 스토리지노드 및 제1임시막의 노출된 표면위에 제2도전층을 형성하는 단계; 상기 제2도전층을 상기 제2임시막과 스토리지노드 및 제1임시막 측벽에만 남도록 선택적으로 제거하여 노드필라를 형성하는 단계; 상기 제1임시막과 제2임시막을 제거하는 단계를 포함하여 이루어진다.A capacitor manufacturing method of a semiconductor device according to the present invention comprises the steps of preparing a semiconductor substrate; Forming a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, respectively; Selectively removing the third insulating layer, the second insulating layer, and the first insulating layer to form a node contact hole; Forming a fourth insulating layer on the third insulating layer including the contact hole; Forming a sidewall by selectively removing the fourth insulating layer so that only the side of the node contact hole remains; Forming a first conductive layer on the exposed surface of the contact hole including the sidewall and the third insulating layer; Forming a fifth insulating film on the first conductive layer; Selectively removing the fifth insulating layer, the first conductive layer, and the third insulating layer except for the node contact hole to form a second temporary layer, a storage node, and a first temporary layer, respectively; Forming a second conductive layer on an exposed surface of the second temporary layer, the storage node, and the first temporary layer; Selectively removing the second conductive layer so as to remain only on sidewalls of the second temporary layer, the storage node, and the first temporary layer; And removing the first and second temporary films.

Description

반도체소자의 커패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2a∼2g도는 본 발명에 따른 반도체소자의 커패시터 제조공정도.2a to 2g is a manufacturing process of the capacitor of the semiconductor device according to the present invention.

Claims (7)

반도체기판을 준비하는 단계; 상기 반도체기판상에 제1절연막과, 상기 제1절연막에 제2절연막 그리고 상기 제3절연막위에 제3절연막을 각각 형성하는 단계; 상기 제3절연막과 제2절연막 및 제1절연막을 선택적으로 제거하여 노드콘택홀을 형성하는 단계; 상기 콘택홀을 포함한 상기 제3절연막위에 제4절연막을 형성하는 단계; 상기 제4절연막을 상기 노드콘택홀 측면에만 남도록 선택적으로 제거하여 측벽을 형성하는 단계; 상기 측벽을 포함한 콘택홀 및 제3절연막의 노출된 표면위에 제1도전층을 형성하는 단계; 상기 제1도전층위에 제5절연막을 형성하는 단계; 상기 노드콘택홀을 제외한 부분의 상기 제5절연막과 제1도전층 및 제3절연막을 선택적으로 제거하여 제2임시막과 스토리지노드 및 제1임시막을 각각 형성하는 단계; 상기 제2임시막과 스토리지노드 및 제1임시막의 노출된 표면위에 제2도전층을 형성하는 단계; 상기 제2도전층을 상기 제2임시막과 스토리지노드 및 제2임시막 측벽에만 남도록 선택적으로 제거하여 노드필라를 형성하는 단계; 상기 제1임시막과 제2임시막을 제거하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 커패시터 제조방법.Preparing a semiconductor substrate; Forming a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the third insulating film, respectively; Selectively removing the third insulating layer, the second insulating layer, and the first insulating layer to form a node contact hole; Forming a fourth insulating layer on the third insulating layer including the contact hole; Forming a sidewall by selectively removing the fourth insulating layer so that only the side of the node contact hole remains; Forming a first conductive layer on the exposed surface of the contact hole including the sidewall and the third insulating layer; Forming a fifth insulating film on the first conductive layer; Selectively removing the fifth insulating layer, the first conductive layer, and the third insulating layer except for the node contact hole to form a second temporary layer, a storage node, and a first temporary layer, respectively; Forming a second conductive layer on an exposed surface of the second temporary layer, the storage node, and the first temporary layer; Selectively removing the second conductive layer so as to remain only on sidewalls of the second temporary layer, the storage node, and the second temporary layer; And removing the first temporary film and the second temporary film. 제1항에 있어서, 상기 제1 및 제3절연막은 산화막을 사용하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein the first and third insulating layers use an oxide film. 제1항에 있어서, 상기 제2 및 제4절연막은 질화막을 사용하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein the second and fourth insulating layers are nitride layers. 제1항에 있어서, 상기 제5절연막은 USG을 사용하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein the fifth insulating layer uses USG. 제1항에 있어서, 상기 노드필라는 제2도전층을 RIE에 의해 선택적으로 제거하여 형성하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein the node pillar is formed by selectively removing the second conductive layer by RIE. 제1항에 있어서, 상기 제1임시막과 제2임시막은 습식식각법에 의해 제거하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein the first and second temporary films are removed by a wet etching method. 제1항에 있어서, 상기 노드필라를 포함한 스토리지노드의 노출된 표면에 유전체막을 형성하는 단계와, 상기 커패시터 유전체막을 포함한 상기 측벽과 제2절연막의 노출된 표면위에 플레이트전극을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, further comprising: forming a dielectric film on an exposed surface of the storage node including the node pillar, and forming a plate electrode on the exposed surface of the sidewall and the second insulating film including the capacitor dielectric film. Capacitor manufacturing method of a semiconductor device, characterized in that formed by. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052217A 1995-12-19 1995-12-19 Method for manufacturing capacitor in semiconductor device KR100348297B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950052217A KR100348297B1 (en) 1995-12-19 1995-12-19 Method for manufacturing capacitor in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950052217A KR100348297B1 (en) 1995-12-19 1995-12-19 Method for manufacturing capacitor in semiconductor device

Publications (2)

Publication Number Publication Date
KR970052821A true KR970052821A (en) 1997-07-29
KR100348297B1 KR100348297B1 (en) 2002-11-29

Family

ID=37488824

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950052217A KR100348297B1 (en) 1995-12-19 1995-12-19 Method for manufacturing capacitor in semiconductor device

Country Status (1)

Country Link
KR (1) KR100348297B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100533959B1 (en) 2004-06-30 2005-12-06 삼성전자주식회사 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
KR100348297B1 (en) 2002-11-29

Similar Documents

Publication Publication Date Title
KR960002851A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970052821A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960005846A (en) Manufacturing Method of Semiconductor Device
KR950007098A (en) DRAM cell manufacturing method
KR950007106A (en) DRAM Cell Capacitor Manufacturing Method
KR970052917A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970052820A (en) Capacitor Manufacturing Method
KR960026870A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960009152A (en) Semiconductor Memory Manufacturing Method
KR960026793A (en) Capacitor Manufacturing Method of Semiconductor Device
KR980012523A (en) Method of manufacturing capacitor
KR970054122A (en) Method for forming storage electrode of semiconductor device
KR970053946A (en) Semiconductor memory device and manufacturing method thereof
KR970054126A (en) Capacitor manufacturing method
KR970052320A (en) Method for forming charge storage electrode of semiconductor device
KR970054549A (en) Capacitor Manufacturing Method of Semiconductor Device
KR930018721A (en) Method for manufacturing capacitor storage electrode of DRAM cell
KR970053995A (en) Capacitor Manufacturing Method of Semiconductor Device
KR950010068A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960043176A (en) Capacitor Manufacturing Method
KR960026856A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026815A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960043192A (en) Semiconductor Capacitors and Manufacturing Method Thereof
KR940016766A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026811A (en) Capacitor Manufacturing Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100624

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee