KR970052917A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970052917A
KR970052917A KR1019950052218A KR19950052218A KR970052917A KR 970052917 A KR970052917 A KR 970052917A KR 1019950052218 A KR1019950052218 A KR 1019950052218A KR 19950052218 A KR19950052218 A KR 19950052218A KR 970052917 A KR970052917 A KR 970052917A
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KR
South Korea
Prior art keywords
conductive layer
forming
film
temporary
insulating
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KR1019950052218A
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Korean (ko)
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KR100348298B1 (en
Inventor
김성철
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문정환
Lg 반도체 주식회사
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Priority to KR1019950052218A priority Critical patent/KR100348298B1/en
Publication of KR970052917A publication Critical patent/KR970052917A/en
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Publication of KR100348298B1 publication Critical patent/KR100348298B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자의 커패시터 제조방법에 관한 것으로, 평탄화 공정시에 주변부에 필라산화막(pillar oxide)을 남긴 상태에서 평탄화공정을 수행하므로써 공정을 단순화 시킬 수 있고, 셀부와 주변부와의 단차를 효과적으로 낮출 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device. The planarization process can be simplified by leaving a pillar oxide in a peripheral part during the planarization process, thereby simplifying the process and effectively reducing the step between the cell part and the peripheral part. I would have to.

본 발명에 따른 반도체 소자의 커패시터 제조방법은 반도체기판을 준비하는 단계; 상기 반도체 기판위에 제1절연막을 중착하는 단계; 상기 제1절연막을 선택적으로 제거하여 노드콘택홀을 형성하는 단계; 상기 콘택홀을 포함한 상기 제1절연막위에 제1도전층을 형성하고 상기 제1도전층을 선택적으로 제거하는 단계; 상기 제1도전층을 포함한 제1절연막위에 제2절연막을 형성하는 단계; 상기 제2절연막과 제1도전층을 선택적으로 제거하여 제1 및 제2임시막과 스토리지노드를 형성하는 단계; 상기 제1 및 2임시막과 스토리지노드를 포함한 제1절연막 위에 제2도전층을 형성하는 단계; 상기 제2도전층을 상기 제2절연막과 상기 제1도전층 측면에만 남도록 선택적으로 제거하여 노드필라를 형성하는 단계; 상기 스토리지노드상에 형성된 제1임시막만 제거하고 상기 노드필라와 스토리지노드의 노출된 표면에 커패시터의 유전체막을 형성하는 단계; 상기 커패시터 유전체막을 포함한 상기 제2임시막 및 1절연막위에 제3도전층을 형성하는 단계; 상기 제3도전층을 포함한 상기 제2임시막위에 제3절연막을 형성하는 단계를 포함하여 이루어진다.A capacitor manufacturing method of a semiconductor device according to the present invention comprises the steps of preparing a semiconductor substrate; Depositing a first insulating film on the semiconductor substrate; Selectively removing the first insulating layer to form a node contact hole; Forming a first conductive layer on the first insulating layer including the contact hole and selectively removing the first conductive layer; Forming a second insulating film on the first insulating film including the first conductive layer; Selectively removing the second insulating layer and the first conductive layer to form first and second temporary layers and a storage node; Forming a second conductive layer on the first insulating layer including the first and second temporary films and the storage node; Selectively removing the second conductive layer so as to remain only on the side surfaces of the second insulating layer and the first conductive layer to form a node pillar; Removing only the first temporary film formed on the storage node and forming a dielectric film of a capacitor on the exposed surface of the node pillar and the storage node; Forming a third conductive layer on the second temporary film and the first insulating film including the capacitor dielectric film; And forming a third insulating film on the second temporary film including the third conductive layer.

Description

반도체 소자의 커패시터 제조방법Capacitor Manufacturing Method for Semiconductor Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2a∼2h도는 본 발명에 따른 반도체 소자의 커패시터 제조공정 단면도.2A to 2H are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the present invention.

Claims (2)

반도체기판을 준비하는 단계; 상기 반도체 기판위에 제1절연막을 중착하는 단계; 상기 제1절연막을 선택적으로 제거하여 노드콘택홀을 형성하는 단계; 상기 콘택홀을 포함한 상기 제1절연막위에 제1도전층을 형성하고 상기 제1도전층을 선택적으로 제거하는 단계; 상기 제1도전층을 포함한 제1절연막위에 제2절연막을 형성하는 단계; 상기 제2절연막과 제1도전층을 선택적으로 제거하여 제1 및 제2임시막과 스토리지노드를 형성하는 단계; 상기 제1 및 2임시막과 스토리지노드를 포함한 제1절연막 위에 제2도전층을 형성하는 단계; 상기 제2도전층을 상기 제2절연막과 상기 제1도전층 측면에만 남도록 선택적으로 제거하여 노드필라를 형성하는 단계; 상기 스토리지노드상에 형성된 제1임시막만 제거하고 상기 노드필라와 스토리지노드의 노출된 표면에 커패시터의 유전체막을 형성하는 단계; 상기 커패시터 유전체막을 포함한 상기 제2임시막 및 1절연막위에 제3도전층을 형성하는 단계; 상기 제3도전층을 포함한 상기 제2임시막위에 제3절연막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.Preparing a semiconductor substrate; Depositing a first insulating film on the semiconductor substrate; Selectively removing the first insulating layer to form a node contact hole; Forming a first conductive layer on the first insulating layer including the contact hole and selectively removing the first conductive layer; Forming a second insulating film on the first insulating film including the first conductive layer; Selectively removing the second insulating layer and the first conductive layer to form first and second temporary layers and a storage node; Forming a second conductive layer on the first insulating layer including the first and second temporary films and the storage node; Selectively removing the second conductive layer so as to remain only on the side surfaces of the second insulating layer and the first conductive layer to form a node pillar; Removing only the first temporary film formed on the storage node and forming a dielectric film of a capacitor on the exposed surface of the node pillar and the storage node; Forming a third conductive layer on the second temporary film and the first insulating film including the capacitor dielectric film; And forming a third insulating film on the second temporary film including the third conductive layer. 제1항에 있어서, 상기 제1임시막은 셀부에 위치하고, 상기 제2임시막은 주변부에 위치하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein the first temporary film is located in the cell part, and the second temporary film is located in the periphery part. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052218A 1995-12-19 1995-12-19 Method for manufacturing capacitor in semiconductor device KR100348298B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950052218A KR100348298B1 (en) 1995-12-19 1995-12-19 Method for manufacturing capacitor in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950052218A KR100348298B1 (en) 1995-12-19 1995-12-19 Method for manufacturing capacitor in semiconductor device

Publications (2)

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KR970052917A true KR970052917A (en) 1997-07-29
KR100348298B1 KR100348298B1 (en) 2002-11-14

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419748B1 (en) * 1996-09-06 2004-06-04 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR100702112B1 (en) * 2000-08-28 2007-03-30 주식회사 하이닉스반도체 Method of forming storage node electrode of semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419748B1 (en) * 1996-09-06 2004-06-04 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR100702112B1 (en) * 2000-08-28 2007-03-30 주식회사 하이닉스반도체 Method of forming storage node electrode of semiconductor memory device

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Publication number Publication date
KR100348298B1 (en) 2002-11-14

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