KR960036065A - Capacitor Formation Method of Semiconductor Device - Google Patents

Capacitor Formation Method of Semiconductor Device Download PDF

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Publication number
KR960036065A
KR960036065A KR1019950006130A KR19950006130A KR960036065A KR 960036065 A KR960036065 A KR 960036065A KR 1019950006130 A KR1019950006130 A KR 1019950006130A KR 19950006130 A KR19950006130 A KR 19950006130A KR 960036065 A KR960036065 A KR 960036065A
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KR
South Korea
Prior art keywords
storage electrode
conductive layer
forming
electrode mask
semiconductor device
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KR1019950006130A
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Korean (ko)
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KR100326808B1 (en
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나원규
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김주용
현대전자산업 주식회사
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Priority to KR1019950006130A priority Critical patent/KR100326808B1/en
Publication of KR960036065A publication Critical patent/KR960036065A/en
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Publication of KR100326808B1 publication Critical patent/KR100326808B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/75Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로, 저장전극 마스크를 이용한 식각공정과 도전체, 유전체의 증착공정을 이용하여 콘택홀을 형성하지 않고 반도체기판에 접속되는 제1도전층을 형성하고 상기 제1도전층의 일측에 접속되는 제2전도층으로 형성되는 캐패시터를 형성하는 동시에 표면적을 증가시킴으로써 고집적화에 충분한 정전용량을 확보하여 반도체소자의 고립적화를 가능하게 하는 기술에 관한 것이다.The present invention relates to a method of forming a capacitor of a semiconductor device, and to form a first conductive layer connected to a semiconductor substrate without forming a contact hole by using an etching process using a storage electrode mask and a deposition process of a conductor and a dielectric. The present invention relates to a technique for forming a capacitor formed of a second conductive layer connected to one side of a first conductive layer and increasing surface area to secure capacitance sufficient for high integration to enable isolation of semiconductor devices.

Description

반도체 소자의 캐패시터 형성방법Capacitor Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 내지 제1D도는 본 발명의 실시예에 따른 반도체소자의 캐패시터 형성공정을 도시한 단면도.1A to 1D are sectional views showing a capacitor forming process of a semiconductor device according to an embodiment of the present invention.

Claims (11)

반도체기판에 접속되는 제1도전층을 형성하는 공장과, 제1저장전극마스크를 이용하여 제1도전층패턴을 형성하는 공장과, 전체표면상부에 제1유전막과 제2도전층을 순차적으로 형성하는 공정과, 제2저장전극마스크를 이용하여 상기 제2도전층과 제1유전체막을 순차적으로 식각하는 공정고, 제3저장전극마스크를 이용하여 상기 제2도전층과 제1유전체막을 식각하여 상기 제1도전층의 일측을 노출시키는 공정과, 전체표면상부에 제2유전체막을 형성하는 공정과, 제4저장전극마스크를 이용하여 상기 제2유전체막을 식각함으로써 상기 일측으로 다시 노출시키는 공정과, 전체표면상부에 제3도전층을 형성함으로써 상기 일측에 접속기키는 공정과, 제5저장전극마스크를 이용하여 상기 제3도전층을 상기 식각하는 공정과, 전체표면상부에 제3유전체막을 형성하는 공정과, 제6저장전극마스크를 이용한 식각공정으로 상기 제1도전층과 제3도전층 그리고 노출되지 않은 하부절연층 계면에만 유전체막을 형성하는 공정과, 전체표면상부에 제4도전층을 형성하는 공정과, 제7저장전극마스크를 이용한 식각공정으로 상기 제4도전층을 식각하여 두층으로 형성된 저장전극을 형성하는 공정을 포함하는 반도체소자의 캐패시터 형성방법.A factory for forming a first conductive layer connected to a semiconductor substrate, a factory for forming a first conductive layer pattern using a first storage electrode mask, and a first dielectric film and a second conductive layer are sequentially formed on the entire surface. And sequentially etching the second conductive layer and the first dielectric layer using a second storage electrode mask, and etching the second conductive layer and the first dielectric layer using a third storage electrode mask. Exposing one side of the first conductive layer, forming a second dielectric film on the entire surface, exposing the second dielectric film back to the one side by etching the second dielectric film using a fourth storage electrode mask, and Forming a third conductive layer on the surface to provide a connection to the one side; etching the third conductive layer using the fifth storage electrode mask; and forming a third dielectric film on the entire surface. And forming a dielectric film only at an interface between the first conductive layer, the third conductive layer and the unexposed lower insulating layer by an etching process using a sixth storage electrode mask, and forming a fourth conductive layer on the entire surface. And forming a storage electrode formed of two layers by etching the fourth conductive layer by an etching process using a seventh storage electrode mask. 제1항에 있어서, 상기 제1. 2. 3. 4도전층은 다결정실리콘막, 폴리사이드 또는 이와 유사한 전도 물질로 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.2. The method of claim 1, wherein said first. 2. 3. A method for forming a capacitor of a semiconductor device, wherein the conductive layer is formed of a polysilicon film, a polyside, or a similar conductive material. 제1항에 있어서, 상기 제1. 3도전층은 저장전극으로 사용되는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.2. The method of claim 1, wherein said first. 3. The method of forming a capacitor of a semiconductor device, characterized in that the conductive layer is used as a storage electrode. 제1항에 있어서, 상기 제2. 4도전층은 플레이트전극으로 사용되는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The method of claim 1, wherein the second. The method of forming a capacitor of a semiconductor device, characterized in that the four conductive layer is used as a plate electrode. 제1항에 있어서, 상기 제1. 2. 3유전체막은 ON 또는 ONO 복합구조로 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.2. The method of claim 1, wherein said first. 2. A method for forming a capacitor of a semiconductor device, characterized in that the three dielectric film is formed in an ON or ONO composite structure. 제1항에 있어서, 상기 제1저장전극마스크는 상기 제5저장전극마스크로 사용되는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The method of claim 1, wherein the first storage electrode mask is used as the fifth storage electrode mask. 제1항에 있어서, 상기 제2저장전극마스크는 상기 제7저장전극마스크로 사용되는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The method of claim 1, wherein the second storage electrode mask is used as the seventh storage electrode mask. 제1항에 있어서, 상기 제3저장전극마스크는 상기 제1저장전극마스크로 사용되는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The method of claim 1, wherein the third storage electrode mask is used as the first storage electrode mask. 제1항에 있어서, 상기 제4저장전극마스크는 상기 제3저장전극마스크보다 상기 제2유전체막의 두께만큼 크게 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The method of claim 1, wherein the fourth storage electrode mask is formed to be larger than the third storage electrode mask by the thickness of the second dielectric layer. 제1항에 있어서, 상기 제6저장전극마스크는 유전체막 식각공정시 상기 제1. 3도전층의 표면에 상기 유전체막이 도포되도록 형성된 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The first storage electrode mask of claim 1, wherein the sixth storage electrode mask is disposed in the dielectric layer etching process. 3. The method of forming a capacitor of a semiconductor device according to claim 1, wherein the dielectric film is coated on the surface of the conductive layer. 3. 제1항에 있어서, 상기 저장전극이 다층으로 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 형성방법.The method of claim 1, wherein the storage electrode is formed in multiple layers. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950006130A 1995-03-22 1995-03-22 Method for fabricating capacitor of semiconductor device KR100326808B1 (en)

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KR1019950006130A KR100326808B1 (en) 1995-03-22 1995-03-22 Method for fabricating capacitor of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950006130A KR100326808B1 (en) 1995-03-22 1995-03-22 Method for fabricating capacitor of semiconductor device

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KR960036065A true KR960036065A (en) 1996-10-28
KR100326808B1 KR100326808B1 (en) 2002-08-08

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