KR970054151A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970054151A
KR970054151A KR1019950069570A KR19950069570A KR970054151A KR 970054151 A KR970054151 A KR 970054151A KR 1019950069570 A KR1019950069570 A KR 1019950069570A KR 19950069570 A KR19950069570 A KR 19950069570A KR 970054151 A KR970054151 A KR 970054151A
Authority
KR
South Korea
Prior art keywords
forming
storage node
silicon nitride
mask pattern
electrode
Prior art date
Application number
KR1019950069570A
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Korean (ko)
Inventor
윤학순
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950069570A priority Critical patent/KR970054151A/en
Publication of KR970054151A publication Critical patent/KR970054151A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 소자의 캐패서터 제조방법을 개시한다. 개시된 본 발명의 방법은 반도체 기판상에 필드 산화막과, 게이트 산화막, 게이트 전극 및 게이트 전극 스페이서를 순차적으로 형성하는 단계; 상기 전체 구조 상부에 층간 절연막을 형성하는 단계; 상기 층간 절연막 상부에 실리콘 질화막을 형성하는 단계; 상기 실리콘 질화막 상부에 스토리지 노드 콘택홀을 형성하기 위한 마스크 패턴을 형성하는 단계; 상기 마스크 패턴의 형태로 식각하는 단계; 상기 전체 구조물 상부에 스토리지 노드 전극을 형성하는 단계; 상기 스토리지 노드 상부에 유전체막을 형성하는 단계; 및 상기 유전체막 상부에 플에이트 전극을 형성하는 단계를 포함한다.The present invention discloses a capacitor manufacturing method of a semiconductor device. The disclosed method comprises sequentially forming a field oxide film, a gate oxide film, a gate electrode and a gate electrode spacer on a semiconductor substrate; Forming an interlayer insulating film on the entire structure; Forming a silicon nitride film on the interlayer insulating film; Forming a mask pattern for forming a storage node contact hole on the silicon nitride layer; Etching in the form of the mask pattern; Forming a storage node electrode on the entire structure; Forming a dielectric layer on the storage node; And forming a flight electrode on the dielectric layer.

Description

반도체 소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (가) 내지 (다)는 본 발명의 일실시예에 다른 반도체 소자의 캐패시터 제조 방법을 보인 요부 단면도.2 (a) to (c) are sectional views showing the principal part of a method of manufacturing a capacitor of a semiconductor device according to one embodiment of the present invention.

Claims (4)

반도체 기판상에 필드 산화막과, 게이트 산화막, 게이트 전극 및 게이트 전극 스페이서를 순차적으로 형성하는 단계; 상기 전체 구조 상부에 층간 절연막을 형성하는 단계; 상기 층간 절연막 상부에 실리콘 질화막을 형성하는 단계; 상기 실리콘 질화막 상부에 스토리지 노드 콘택홀을 형성하기 위한 마스크 패턴을 형성하는 단계; 상기 마스크 패턴의 형태로 식각하는 단계; 상기 전체 구조물 상부에 스토리지 노드 전극을 형성하는 단계; 상기 스토리지 노드 상부에 유전체막을 형성하는 단계; 및 상기 유전체막 상부에 플에이트 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.Sequentially forming a field oxide film, a gate oxide film, a gate electrode, and a gate electrode spacer on the semiconductor substrate; Forming an interlayer insulating film on the entire structure; Forming a silicon nitride film on the interlayer insulating film; Forming a mask pattern for forming a storage node contact hole on the silicon nitride layer; Etching in the form of the mask pattern; Forming a storage node electrode on the entire structure; Forming a dielectric layer on the storage node; And forming a plate electrode on the dielectric layer. 제1항에 있어서, 상기 마스크 패턴은 게이트 측벽 스페이서와 필드 산화막의 버드빅 부분을 포함하고 있는 실리콘 질화막이 노출되도록 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the mask pattern is formed to expose a silicon nitride film including a gate sidewall spacer and a budbig portion of a field oxide film. 제1항 또는 제2항에 있어서, 상기 실리콘 질화막의 두께는 500 내지 1000Å인 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of manufacturing a capacitor of a semiconductor device according to claim 1 or 2, wherein the silicon nitride film has a thickness of 500 to 1000 mW. 제1항 또는 있어서, 상기 스토리지 노드 전극용 폴리실리콘의 두께는 1000 내지 2000Å인 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the thickness of the polysilicon for storage node electrodes is 1000 to 2000 microns. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069570A 1995-12-30 1995-12-30 Capacitor Manufacturing Method of Semiconductor Device KR970054151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950069570A KR970054151A (en) 1995-12-30 1995-12-30 Capacitor Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069570A KR970054151A (en) 1995-12-30 1995-12-30 Capacitor Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR970054151A true KR970054151A (en) 1997-07-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950069570A KR970054151A (en) 1995-12-30 1995-12-30 Capacitor Manufacturing Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR970054151A (en)

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