KR970030485A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970030485A
KR970030485A KR1019950040712A KR19950040712A KR970030485A KR 970030485 A KR970030485 A KR 970030485A KR 1019950040712 A KR1019950040712 A KR 1019950040712A KR 19950040712 A KR19950040712 A KR 19950040712A KR 970030485 A KR970030485 A KR 970030485A
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KR
South Korea
Prior art keywords
insulating layer
forming
layer
conductive layer
insulating
Prior art date
Application number
KR1019950040712A
Other languages
Korean (ko)
Inventor
문철연
Original Assignee
김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950040712A priority Critical patent/KR970030485A/en
Publication of KR970030485A publication Critical patent/KR970030485A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

큰 커패시턴스를 커패시터를 효과적으로 제조할 수 있는 반도체장치의 커패시터 제조방법에 관하여 개시한다. 본 발명은 반도체 기판상에 제1 절연층, 제2 절연층 및 제3 절연층을 형성하는 단계와, 상기 제3 절연층을 패터닝하여 제3 절연층 패턴을 형성하는 단계와, 상기 제3 절연층 및 제2 절연층 상에 제1 도전층을 형성하는 단계와, 상기 제1 도전층 상에 절연물질을 형성한후 이방성식각하여 상기 제3 절연층 패턴의 측벽 상부에 제4 절연층으로 스페이서를 형성하는 단계와, 상기 스페이서에 의해 노출된 제1 도전층, 제2 전연층 및 제1 절연층을 이방성식각하여 상기 기판을 노출하는 콘택홀을 형성하는 단계와, 상기 콘택홀을 매립하도록 기판의 전면에 제2 도전층을 형성하는 단계와, 상기 제2 도전층에 의해 마련되는 오목부위에 제5 절연층을 형성하는 단계와, 상기 제5 절연층을 마스크로 상기 제2 도전층 및 제1 도전층을 식각하는 단계와, 상기 제5 질연층, 제4 질연층 및 제3 절연층을 식각하여 실리더형의 스토리지 전극을 형성하는 단계와, 상기 스토리지 전극이 형성된 기판의 전면에 유전막 및 플레이트 전극을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 커패시터 제조방법을 제공한다. 본 발명에 의하면, 종래의 실린더형 커패시터보다 동일한 면적에서 보다 큰 커패시턴스를 갖는 커패시터를 효과적으로 제조할 수 있다.Disclosed is a method of manufacturing a capacitor of a semiconductor device capable of effectively manufacturing a capacitor with large capacitance. The present invention provides a method of forming a third insulating layer pattern by forming a first insulating layer, a second insulating layer, and a third insulating layer on a semiconductor substrate, by patterning the third insulating layer, and forming the third insulating layer pattern. Forming a first conductive layer on the second and second insulating layers; Forming a contact hole for exposing the substrate by anisotropically etching the first conductive layer, the second leading layer, and the first insulating layer exposed by the spacer; Forming a second conductive layer on the entire surface of the substrate, forming a fifth insulating layer on a recess provided by the second conductive layer, and using the fifth insulating layer as a mask for the second conductive layer and the second conductive layer. Etching the first conductive layer, and the fifth nitride layer and the fourth conductive layer Forming a storage electrode of a cylinder type by etching the nitride layer and the third insulating layer, and forming a dielectric layer and a plate electrode on the entire surface of the substrate on which the storage electrode is formed. It provides a manufacturing method. According to the present invention, a capacitor having a larger capacitance in the same area than a conventional cylindrical capacitor can be effectively manufactured.

Description

반도체 장치의 커패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제6도 내지 제9도는 본 발명에 의한 반도체장치의 커패시터 제조방법을 설명하기 위하여 도시한 단면도들이다.6 to 9 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

Claims (5)

반도체 기판상에 제1 절연층, 제2 절연층 및 제3 절연층을 형성하는 단계; 상기 제3 절연층을 패터닝하여 제3 절연층 패턴을 형성하는 단계; 상기 제3 절연층 및 제2 절연층 상에 제1 도전층을 형성하는 단계; 상기 제1 도전층 상에 절연물질을 형성한후 이방성식각하여 상기 제3 절연층 패턴의 측벽 상부에 제4 절연층으로 스페이서를 형성하는 단계; 상기 스페이서에 의해 노출된 제1 도전층, 제2 절연층 및 제1 절연층을 이방성식각하여 상기 기판을 노출하는 콘택홀을 형성하는 단계; 상기 콘택홀을 매립하도록 기판의 전면에 제2 도전층을 형성하는 단계; 상기 제2 도전층에 의해 마련되는 오목부위에 제5 절연층을 형성하는 단계; 상기 제5 절연층을 마스크로 상기 제2 도전층 및 제1 도전층을 식각하는 단계; 상기 제5 절연층, 제4 절연층 및 제3 절연층을 식각하여 실리더형의 스토리지 전극을 형성하는 단계; 및 상기 스토리지 전극이 형성된 기판의 전면에 유전막 및 플에이트 전극을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.Forming a first insulating layer, a second insulating layer, and a third insulating layer on the semiconductor substrate; Patterning the third insulating layer to form a third insulating layer pattern; Forming a first conductive layer on the third insulating layer and the second insulating layer; Forming an insulating material on the first conductive layer and then anisotropically etching the spacer to form a spacer as a fourth insulating layer on an upper sidewall of the third insulating layer pattern; Anisotropically etching the first conductive layer, the second insulating layer, and the first insulating layer exposed by the spacer to form a contact hole exposing the substrate; Forming a second conductive layer on an entire surface of the substrate to fill the contact hole; Forming a fifth insulating layer on the recess provided by the second conductive layer; Etching the second conductive layer and the first conductive layer using the fifth insulating layer as a mask; Etching the fifth insulating layer, the fourth insulating layer, and the third insulating layer to form a cylinder type storage electrode; And forming a dielectric film and a flight electrode on the entire surface of the substrate on which the storage electrode is formed. 제1항에 있어서, 상기 제1 절연층 및 제3 절연층, 제4 절연층은 불순물이 도우핑된 산확막이나 도우핑되지 않은 산화막인 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 1, wherein the first insulating layer, the third insulating layer, and the fourth insulating layer are acid diffusion films doped with impurities or undoped oxide films. 제1항에 있어서, 상기 제2 절연층은 질화막인 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.The method of claim 1, wherein the second insulating layer is a nitride film. 제1항에 있어서, 제5 절연층은 SOG막, 포토레지스트막 및 BPSG막 중에서 선택된 어느 하나인 막인 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.The method of claim 1, wherein the fifth insulating layer is a film selected from an SOG film, a photoresist film, and a BPSG film. 제1항에 있어서, 상기 제1 도전층 및 제2 도전층은 불순물이 도핑된 다결정 실리콘막인 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 1, wherein the first conductive layer and the second conductive layer are polycrystalline silicon films doped with impurities.
KR1019950040712A 1995-11-10 1995-11-10 Capacitor Manufacturing Method of Semiconductor Device KR970030485A (en)

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KR1019950040712A KR970030485A (en) 1995-11-10 1995-11-10 Capacitor Manufacturing Method of Semiconductor Device

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Application Number Priority Date Filing Date Title
KR1019950040712A KR970030485A (en) 1995-11-10 1995-11-10 Capacitor Manufacturing Method of Semiconductor Device

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KR970030485A true KR970030485A (en) 1997-06-26

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100756806B1 (en) * 2001-06-29 2007-09-10 주식회사 하이닉스반도체 A method for forming a capacitor of a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100756806B1 (en) * 2001-06-29 2007-09-10 주식회사 하이닉스반도체 A method for forming a capacitor of a semiconductor device

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