KR970052485A

KR970052485A - Method for manufacturing storage electrodes of capacitor

Info

Publication number: KR970052485A
Application number: KR1019950066975A
Authority: KR
Inventors: 이현덕
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-29
Filing date: 1995-12-29
Publication date: 1997-07-29

Abstract

본 발명은 스토리지전극의 형상을 실린더형으로 유효 커패시터 면적을 증가시킬 수 있도록 하는 커패시터의 스토리지전극 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a storage electrode of a capacitor to increase the effective capacitor area in a cylindrical shape of the storage electrode.

상기 목적을 달성하기 위하여 본 발명은, 반도체기판 상에 제1산화막을 형성한 후 부분적으로 식각하여 상기 반도체기판의 소정부위를 노출시키는 콘택홀을 형성하는 제1단계; 상기 결과물 상에 제1도전층을 형성하고, 상기 제1산화막의 상면이 노출되도록 상기 제1도전층을 화학기계폴리싱(CMP) 방법으로서 폴리싱하는 제2단계; 상기 결과물 전면에 제2산화막을 형성하고, 상기 콘택홀 내부의 도프드 폴리실리콘(doped poly Si)이 노출되도록 상기 제2산화막의 일부를 식각하여 제2산화막패턴을 형성하는 제3단계; 상기 결과물 상에 제1폴리실리콘층 및 제3산화막을 순차적으로 형성하는 제4단계; 및 상기 제2산화막패턴의 상면이 노출되도록 상기 제3산화막 및 제1폴리실리콘층을 화학기계폴리싱(CMP) 방법으로 폴리싱한 후, 제3산화막패턴 및 제2산화막패턴을 제거하는 제5단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention includes a first step of forming a contact hole for exposing a predetermined portion of the semiconductor substrate by partially etching after forming the first oxide film on the semiconductor substrate; Forming a first conductive layer on the resultant, and polishing the first conductive layer by a chemical mechanical polishing (CMP) method such that an upper surface of the first oxide film is exposed; Forming a second oxide layer on the entire surface of the resultant, and etching a portion of the second oxide layer to expose a doped poly silicon in the contact hole to form a second oxide layer pattern; A fourth step of sequentially forming a first polysilicon layer and a third oxide film on the resultant product; And polishing the third oxide layer and the first polysilicon layer by chemical mechanical polishing (CMP) to expose the top surface of the second oxide layer pattern, and then removing the third oxide layer pattern and the second oxide layer pattern. It is characterized by comprising.

Description

Method for manufacturing storage electrode of capacitor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2E도는 이중 실린더 스택 커패시터를 제조하는 경우를 설명하기 위한 단면도들이다.2A through 2E are cross-sectional views illustrating a case of manufacturing a double cylinder stack capacitor.

Claims

Forming a contact hole exposing a predetermined portion of the semiconductor substrate by partially etching the first oxide layer on the semiconductor substrate; Forming a first conductive layer on the resultant, and polishing the first conductive layer by a chemical mechanical polishing (CMP) method such that an upper surface of the first oxide film is exposed; Forming a second oxide layer on the entire surface of the resultant, and etching a portion of the second oxide layer to expose a doped poly silicon in the contact hole to form a second oxide layer pattern; A fourth step of sequentially forming a first polysilicon layer and a third oxide film on the resultant product; And polishing the third oxide layer and the first polysilicon layer by chemical mechanical polishing (CMP) to expose the top surface of the second oxide layer pattern, and then removing the third oxide layer pattern and the second oxide layer pattern. Storage electrode manufacturing method of a capacitor, characterized in that comprises.

The method of claim 1, wherein in the fourth step, after forming the first polysilicon layer, an oxide spacer is formed on the stepped portion of the first polysilicon layer, and then the second polysilicon layer and the third oxide layer are sequentially formed. Method for manufacturing a storage electrode of a capacitor, characterized in that forming.

※ Note: The disclosure is based on the initial application.