KR970072419A - Method of manufacturing capacitor - Google Patents

Method of manufacturing capacitor Download PDF

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Publication number
KR970072419A
KR970072419A KR1019960012553A KR19960012553A KR970072419A KR 970072419 A KR970072419 A KR 970072419A KR 1019960012553 A KR1019960012553 A KR 1019960012553A KR 19960012553 A KR19960012553 A KR 19960012553A KR 970072419 A KR970072419 A KR 970072419A
Authority
KR
South Korea
Prior art keywords
forming
insulating film
storage electrode
layer
semiconductor substrate
Prior art date
Application number
KR1019960012553A
Other languages
Korean (ko)
Inventor
오승영
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960012553A priority Critical patent/KR970072419A/en
Publication of KR970072419A publication Critical patent/KR970072419A/en

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

반도체 장치에서의 단차를 증가시키지 않으면서 스토리지 전극의 유효 면적을 증가시켜서 후속 배선 공정이 용이한 커패시터 제조 방법을 제공한다. 본 발명은 반도체 기판에 제1절연막·식각 저지층 및 제2절연막을 증착하는 단계와, 사진 식각 공정을 이용하여 상기 제2절연막·상기 식각 저치층 및 상기 제1절연막을 관통하여 상기 반도체 기판의 표면을 대기중에 노출하는 접촉창을 형성하는 단계와, 상기 식각 저지층 보다 낮게 상기 접촉창 내벽에 스페이서를 형성하는 단계와, 상기 제1절연막을 식각하는 단계와, 상기 접촉창을 통하여 상기 반도체 기판에 접촉하는 도전층을 상기 제2절연막 위에 형성하는 단계와, 상기 도전층을 패터닝하여 스토리지 전극을 형성하는 단계와, 상기 스토리지 전극의 표면에 유전체막 및 플레이트 전극을 형성하는 단계를 포함하는 반도체 장치의 커패시터 제조 방법이다. 따라서, 본 발명의 방법에 의해서 스토리지 전극의 유효면적을 넓히면서 메모리 셀의 단차를 증가시키지 않은 커패시터를 형성하여 후속 배선 공정을 용이하게 할수 있다.There is provided a method of manufacturing a capacitor in which a subsequent wiring process is facilitated by increasing the effective area of a storage electrode without increasing a step in a semiconductor device. The present invention relates to a method of manufacturing a semiconductor device, comprising: depositing a first insulating film, an etching stopper layer and a second insulating film on a semiconductor substrate; and forming a second insulating film on the semiconductor substrate through the second insulating film, A method of manufacturing a semiconductor device, comprising: forming a contact window that exposes a surface of the semiconductor substrate to the atmosphere; forming a spacer on an inner wall of the contact window lower than the etch stop layer; etching the first insulating film; Forming a conductive layer in contact with the first insulating film on the second insulating film; patterning the conductive layer to form a storage electrode; and forming a dielectric film and a plate electrode on the surface of the storage electrode / RTI > Therefore, by the method of the present invention, the capacitor can be formed without increasing the step of the memory cell while widening the effective area of the storage electrode, thereby facilitating the subsequent wiring process.

Description

커패시터의 제조 방법Method of manufacturing capacitor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제4도는 본 발명에 의하여 커패시터의 제조 방법을 설명하기 위한 단면도들이다.FIG. 4 is a cross-sectional view illustrating a method of manufacturing a capacitor according to the present invention.

Claims (1)

스토리지 전극·유전체막 및 플레이트 전극을 구비하는 반도체 장치의 커패시터 제조 방법에 있어서, 반도체 기판에 제1절연막을 증착하는 단계; 상기 제1절연막 위에 식각 저치층을 증착하는 단계; 상기 식각 저지층 위에 제2절연막을 증착하는 단계; 사진 식각 공정을 이용하여 상기 제2절연막·상기 식각 저지층 및 상기 제1절연막을 관통하여 상기 반도체 기판의 표면을 대기 중에 노출하는 접촉창을 형성하는 단계; 상기 식각 저지층 보다 낮게 상기 접촉창 내벽에 스페이서를 형성하는 단계; 상기 제1절연막을 저지하는 단계; 상기 접촉창을 통하여 상기 반도체 기판에 접촉하는 도전층을 상기 제2절연막 위에 형성하는 단계; 상기 도전층을 패터닝하여 스토리지 전극을 형성하는 단계; 상기 스토리지 전극의 표면에 유전체막을 형성하는 단계; 및 상기 유전체막의 표면에 플레이트 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 커패시터 제조 방법.A method of manufacturing a capacitor of a semiconductor device having a storage electrode / dielectric film and a plate electrode, comprising the steps of: depositing a first insulating film on a semiconductor substrate; Depositing an etch lower layer over the first insulating layer; Depositing a second insulating layer on the etch stop layer; Forming a contact window through the second insulating layer, the etching stop layer, and the first insulating layer using a photolithography process to expose the surface of the semiconductor substrate to the atmosphere; Forming a spacer on the inner wall of the contact window lower than the etch stop layer; Blocking the first insulating film; Forming a conductive layer on the second insulating film in contact with the semiconductor substrate through the contact window; Forming a storage electrode by patterning the conductive layer; Forming a dielectric film on a surface of the storage electrode; And forming a plate electrode on a surface of the dielectric film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960012553A 1996-04-24 1996-04-24 Method of manufacturing capacitor KR970072419A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960012553A KR970072419A (en) 1996-04-24 1996-04-24 Method of manufacturing capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960012553A KR970072419A (en) 1996-04-24 1996-04-24 Method of manufacturing capacitor

Publications (1)

Publication Number Publication Date
KR970072419A true KR970072419A (en) 1997-11-07

Family

ID=66216752

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960012553A KR970072419A (en) 1996-04-24 1996-04-24 Method of manufacturing capacitor

Country Status (1)

Country Link
KR (1) KR970072419A (en)

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