KR970007791B1 - Process for manufacturing capacitor of semiconductor - Google Patents

Abstract

A method for manufacturing capacitor of semiconductor comprising the step etching the second, the first isolation membranes in contact regions by using store-electrode contact mask to form contact holes after forming the first, the second isolation membranes on a wafer; the step depositing the first conducting layer on said second isolation membrane and said contact holes; the step forming the third isolation membrane in prescribed thickness on the second conducting layer; the step etching said third isolation membrane in constant thickness by using anisotropy etching process to expose the second conducting layer under the contact holes; the step depositing the second conducting layer to contact to the first conducting layer; the step coating the forth isolation membrane on the second conducting layer to filling said contact holes; the step etching said forth isolation membrane in constant thickness by etchback process to expose the second conducting layer on the contact holes; the step depositing the third conducting layer, and then forming store-electrode mask on the third conducting layer; the step etching the third, second and first conducting layers and the forth, third isolation layers without store-electrode mask in their sequence; and the step etching remnant the forth, third isolation layers and the second isolation layer by wet etching method to form store-electrode consisted of the first, second and third conductor patterns is disclosed. Thereby, the capacity of the capacitor is increased. Further, a capacitor having sufficient capacity is provided by simple process through controlling of step coverage of low temperature thin membrane