KR930008893B1 - Capacitor manufacturing method of memory cell - Google Patents

Abstract

The memory-cell capacitor is prepared by forming a field oxide film, gate and bit lines on a substrate, depositing a thin oxide film after insulating the bit line with a silicon oxide film, etching a node contact, depositing polycrystalline silicon, pattering with a small mask and etching polycrystalline silicon at the pillar-forming area for node, removing the photo sensitive solution, depositing polycrystalline silicon for node, depositing and etch-backing the silicon oxide film to display polycrystalline silicon for node, etching the displayed silicon, removing the oxide film, forming dielectric film and depositing plate polycrystalline silicon.

Description

Capacitor Manufacturing Method of Memory Cell

1 is a view showing a capacitor manufacturing method of the prior art.

2 is a view showing a capacitor manufacturing method of the present invention.

* Explanation of symbols for main parts of the drawings

1: gate 2: bit line

3: Selective Polycrystalline Silicon 4: Polycrystalline Silicon for Node

5: polycrystalline silicon for plate 6: silicon oxide film

8: photosensitive agent 9: silicon nitride film

10: dielectric

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a memory cell, and more particularly to a method of manufacturing a capacitor of a memory cell, which has a capacitor cylinder shape and is suitable for a simple and highly integrated cell.

In the prior art (for example, Hitachi's retention technology), the following process was used to manufacture the capacitor of the memory cell.

That is, as shown in FIG. 1A, the gate 1 and bit line 2 patterns are formed on the silicon substrate, and polycrystalline silicon 3 is selectively deposited on the node contacts. Thereafter, the silicon nitride film 9 and the silicon nitride film 6 are sequentially deposited, and a pillar pattern is formed. Subsequently, as shown in FIG. 1B, the silicon oxide film and the nitride film are etched and the photosensitive agent is removed. At this time, when the nitride film is etched, a high selectivity with the oxide film is required.

Subsequently, the polycrystalline silicon 4 for the node is deposited as shown in FIG. 1C and planarized with an oxide film or SOG, and then etched as in FIG. 1D to remove the polycrystalline silicon between the nodes, thereby separating the cells. A capacitor is then formed by coating a dielectric film and depositing plate polycrystalline silicon.

Such a conventional technology has the following problems. Firstly, selective polycrystalline silicon deposition requires high technology and expensive equipment, and secondly, planarization into silicon nitride film is difficult and requires many new technologies. Third, silicon nitride etching requires high selectivity with oxide and also the shape of pillar must be vertical, which is a very difficult technique in mass production.

Capacitor manufacturing method of the present invention is devised to solve this problem will be described with reference to the accompanying drawings, Figure 2 as follows.

First, as shown in FIG. 2A, the field oxide gate 1 and the bit line 2 are formed on a silicon substrate, the bit line 2 is insulated with the silicon oxide film 6, and then the thin silicon oxide film 6 is again formed. Is deposited.

After etching the node contacts, doped polycrystalline silicon 4 is deposited.

At this time, the doped polycrystalline silicon 4 is deposited to about 1000 ~ 1500 ~. Subsequently, as shown in FIG. 2B, the polycrystalline silicon 4 is etched after forming a pattern using a small mask in the area where the pillar forming pillar is to be formed. Then, the photosensitive agent 8 is removed like FIG. 2C (FIG. 2D). As shown in FIG. 2E, the polycrystalline silicon 4 for node formation is deposited, and the silicon oxide film 6 is deposited and etched back so that the polycrystalline silicon is exposed (FIG. 2f). Is etched and the oxide film 6 is removed from hydrofluoric acid (HF) (Fig. 2g).

A dielectric film 10 is then formed and plate polycrystalline silicon 5 is deposited to complete the capacitor of the memory cell.

As described above, since a memory cell capacitor is manufactured by the method of the present invention, a technique having a high selectivity with a silicon oxide film during pillar formation by selective polycrystalline silicon deposition technology, silicon nitride film planarization technology, and silicon nitride film etching is a problem of the prior art. A capacitor of a memory cell can be manufactured by a technology that can avoid the cost and practical mass production.

Claims (1)

A method of manufacturing a capacitor of a memory cell, the method comprising: forming a field oxide layer, a gate, and a bit line on a silicon substrate, insulating the bit line with the silicon oxide layer, and depositing a thin oxide layer again, and etching the node contact. (B) depositing the doped polycrystalline silicon, forming a pattern using a small mask in the region where the node forming filter is to be formed, and etching the polycrystalline silicon (c), removing the photoresist, Depositing and planarizing an oxide film to form a pillar pattern pillar pattern and etching the oxide film; removing photoresist and depositing polycrystalline silicon for node formation; (e) depositing a silicon oxide film to etch back Therefore, after exposing the polycrystalline silicon for forming a node, the exposed polycrystalline silicon is etched and the oxide film is removed (f), and a dielectric film is formed. The method of the memory cell capacitor formed by a step (g) depositing a polysilicon rate.