KR960008528B1 - Manufacturing method of capacitor - Google Patents
Manufacturing method of capacitor Download PDFInfo
- Publication number
- KR960008528B1 KR960008528B1 KR92026712A KR920026712A KR960008528B1 KR 960008528 B1 KR960008528 B1 KR 960008528B1 KR 92026712 A KR92026712 A KR 92026712A KR 920026712 A KR920026712 A KR 920026712A KR 960008528 B1 KR960008528 B1 KR 960008528B1
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- formating
- cavity
- barrier
- silicon layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
The capacitor manufacturing method comprises the steps of: formating a barrier between layers, a contact hole for exposing silicon substrates on a designated area, a first ploy silicon layer, and a first. PR pattern for a cavity on the first poly silicon layer in turn; depositing a barrier on an entire structure; formating a second PR pattern for a cavity mask; etching the exposed barrier for patterning a cavity barrier; removing the first and second PR layer patterns for formating the first cavity; depositing second poly silicon layer on the barrier pattern within a certain thickness; formating a third PR pattern of a storing electrode and etching the exposed pattern of the second poly silicon layer; formating second cavity by wet etching of the cavity barrier pattern; and formating a poly silicon pattern by dry etching of the expose first poly silicon layer to make the storing electrode having first and second cavities.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR92026712A KR960008528B1 (en) | 1992-12-30 | 1992-12-30 | Manufacturing method of capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR92026712A KR960008528B1 (en) | 1992-12-30 | 1992-12-30 | Manufacturing method of capacitor |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940016828A KR940016828A (en) | 1994-07-25 |
KR960008528B1 true KR960008528B1 (en) | 1996-06-26 |
Family
ID=19347847
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR92026712A KR960008528B1 (en) | 1992-12-30 | 1992-12-30 | Manufacturing method of capacitor |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960008528B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100236066B1 (en) * | 1996-10-18 | 1999-12-15 | κΉμν | Capacitor structure in semiconductor device and manufacturing method thereof |
-
1992
- 1992-12-30 KR KR92026712A patent/KR960008528B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR940016828A (en) | 1994-07-25 |
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G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20060522 Year of fee payment: 11 |
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LAPS | Lapse due to unpaid annual fee |