KR960008526B1 - Manufacturing method of capacitor - Google Patents

Manufacturing method of capacitor Download PDF

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Publication number
KR960008526B1
KR960008526B1 KR92006806A KR920006806A KR960008526B1 KR 960008526 B1 KR960008526 B1 KR 960008526B1 KR 92006806 A KR92006806 A KR 92006806A KR 920006806 A KR920006806 A KR 920006806A KR 960008526 B1 KR960008526 B1 KR 960008526B1
Authority
KR
South Korea
Prior art keywords
interface layer
layer
forming
forth
semiconductor layer
Prior art date
Application number
KR92006806A
Other languages
Korean (ko)
Other versions
KR930022554A (en
Inventor
Young-Kwon Chon
Original Assignee
Lg Semicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Semicon Co Ltd filed Critical Lg Semicon Co Ltd
Priority to KR92006806A priority Critical patent/KR960008526B1/en
Publication of KR930022554A publication Critical patent/KR930022554A/en
Application granted granted Critical
Publication of KR960008526B1 publication Critical patent/KR960008526B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

forming a first semiconductor layer (24), a first interface layer (25), a second semiconductor layer (26), a second interface layer (27), a third semiconductor layer (28) and a third interface layer (29) in sequence after forming a contact hole by etching the first, the second, and the third insulating layer (21, 22, 23) properly; forming a forth interface layer (31) after etching the first semiconductor layer (24) to the third interface layer (29) selectively and forming a forth semiconductor layer (30), and etching the forth semiconductor layer (30) by using the third interface layer (29) as mask in order to reveal the third interface layer (29), and removing the third and the forth interface layer (29, 31); etching the second, the third, the forth semiconductor layer and the second interface layer selectively using the side wall of the fifth interface layer (32) as mask after forming the side wall of the fifth interface layer (32) by deposition and etchback of the fifth interface layer; forming a storage electrode by removing the first, the second and the fifth interface layer, and forming a plate electrode over the whole wafer after depositing a dielectric over the whole face of the storage electrode.
KR92006806A 1992-04-22 1992-04-22 Manufacturing method of capacitor KR960008526B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92006806A KR960008526B1 (en) 1992-04-22 1992-04-22 Manufacturing method of capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92006806A KR960008526B1 (en) 1992-04-22 1992-04-22 Manufacturing method of capacitor

Publications (2)

Publication Number Publication Date
KR930022554A KR930022554A (en) 1993-11-24
KR960008526B1 true KR960008526B1 (en) 1996-06-26

Family

ID=19332164

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92006806A KR960008526B1 (en) 1992-04-22 1992-04-22 Manufacturing method of capacitor

Country Status (1)

Country Link
KR (1) KR960008526B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3532325B2 (en) * 1995-07-21 2004-05-31 株式会社東芝 Semiconductor storage device

Also Published As

Publication number Publication date
KR930022554A (en) 1993-11-24

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