KR960010053B1 - Contact manufacturing method of semiconductor device - Google Patents

Contact manufacturing method of semiconductor device Download PDF

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Publication number
KR960010053B1
KR960010053B1 KR92023040A KR920023040A KR960010053B1 KR 960010053 B1 KR960010053 B1 KR 960010053B1 KR 92023040 A KR92023040 A KR 92023040A KR 920023040 A KR920023040 A KR 920023040A KR 960010053 B1 KR960010053 B1 KR 960010053B1
Authority
KR
South Korea
Prior art keywords
forming
photoresist
substrate
semiconductor device
etching
Prior art date
Application number
KR92023040A
Other languages
Korean (ko)
Other versions
KR940016479A (en
Inventor
Jin-Woong Kim
Kon Sonn
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Priority to KR92023040A priority Critical patent/KR960010053B1/en
Publication of KR940016479A publication Critical patent/KR940016479A/en
Application granted granted Critical
Publication of KR960010053B1 publication Critical patent/KR960010053B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

forming wordline comprising a gate oxide layer (3), a gate poly (4), a mask oxide layer (5) and an oxide spacer (7) on the substrate (1); depositing three layered photoresist comprising the down (12), the middle (13) and the upper photoresistes (14); patterning the down photoresist by exposing and etching; forming a photoresist pattern after forming an insulating layer on the top of the substrate; forming a contact hole (19) by removing the photoresist pattern and the down photoresist (12) after etching the revealed insulating layer; forming a conducting layer (20) contacted to the down substrate through the contact hole.
KR92023040A 1992-12-02 1992-12-02 Contact manufacturing method of semiconductor device KR960010053B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92023040A KR960010053B1 (en) 1992-12-02 1992-12-02 Contact manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92023040A KR960010053B1 (en) 1992-12-02 1992-12-02 Contact manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR940016479A KR940016479A (en) 1994-07-23
KR960010053B1 true KR960010053B1 (en) 1996-07-25

Family

ID=19344496

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92023040A KR960010053B1 (en) 1992-12-02 1992-12-02 Contact manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR960010053B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557593B1 (en) * 2004-05-24 2006-03-03 엘지전자 주식회사 Polymer resist pattern manufacturing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100587036B1 (en) * 1999-10-25 2006-06-07 주식회사 하이닉스반도체 Contact formation method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557593B1 (en) * 2004-05-24 2006-03-03 엘지전자 주식회사 Polymer resist pattern manufacturing method

Also Published As

Publication number Publication date
KR940016479A (en) 1994-07-23

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Payment date: 20100624

Year of fee payment: 15

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