KR960008570B1 - Semiconductor memory device and the manufacturing method - Google Patents

Semiconductor memory device and the manufacturing method Download PDF

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Publication number
KR960008570B1
KR960008570B1 KR93000964A KR930000964A KR960008570B1 KR 960008570 B1 KR960008570 B1 KR 960008570B1 KR 93000964 A KR93000964 A KR 93000964A KR 930000964 A KR930000964 A KR 930000964A KR 960008570 B1 KR960008570 B1 KR 960008570B1
Authority
KR
South Korea
Prior art keywords
forming
epilayer
over
conducting layer
pattern
Prior art date
Application number
KR93000964A
Other languages
Korean (ko)
Other versions
KR940018981A (en
Inventor
Sung-Tae Kim
Kyung-Hoon Kim
Sung-Hoon Kang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to KR93000964A priority Critical patent/KR960008570B1/en
Publication of KR940018981A publication Critical patent/KR940018981A/en
Application granted granted Critical
Publication of KR960008570B1 publication Critical patent/KR960008570B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

forming a contact hole over a first insulating layer (83); forming a first conducting layer over the insulating layer (83); forming a first epilayer over the first conducting layer; forming a first side wall spacer (89) with a third material on the side wall of the pattern of the second epilayer; patterning the first epilayer and the first conducting layer; forming i-HSG(island-Hemi Spherical Grain) (91) with a second conducting material after removing the second epilayer; forming a second side wall spacer (93') to keep i-HSG from etching and patterning the first epilayer; forming micro pillars inside a cylinder by etching the pattern of the first conducting layer using the pattern of the second epilayer as mask; depositing a dielectric (97) over the whole surface of the wafer after removing the first and the second spacer (89, 93'); depositing a second conducting layer over the dielectric (97).
KR93000964A 1993-01-27 1993-01-27 Semiconductor memory device and the manufacturing method KR960008570B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93000964A KR960008570B1 (en) 1993-01-27 1993-01-27 Semiconductor memory device and the manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93000964A KR960008570B1 (en) 1993-01-27 1993-01-27 Semiconductor memory device and the manufacturing method

Publications (2)

Publication Number Publication Date
KR940018981A KR940018981A (en) 1994-08-19
KR960008570B1 true KR960008570B1 (en) 1996-06-28

Family

ID=19350002

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93000964A KR960008570B1 (en) 1993-01-27 1993-01-27 Semiconductor memory device and the manufacturing method

Country Status (1)

Country Link
KR (1) KR960008570B1 (en)

Also Published As

Publication number Publication date
KR940018981A (en) 1994-08-19

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